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X9110TV14I PDF预览

X9110TV14I

更新时间: 2024-09-23 22:12:23
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英特矽尔 - INTERSIL /
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描述
Single Digitally-Controlled (XDCP) Potentiometer

X9110TV14I 数据手册

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X9110  
®
Dual Supply/Low Power/1024-Tap/SPI Bus  
Data Sheet  
October 7, 2005  
FN8158.2  
Single Digitally-Controlled (XDCP™)  
Potentiometer  
Features  
• 1024 Resistor Taps – 10-Bit Resolution  
The X9110 integrates a single digitally controlled  
potentiometer (XDCP) on a monolithic CMOS integrated  
circuit.  
• SPI Serial Interface for write, read, and transfer operations  
of the potentiometer  
• Wiper Resistance, 40Typical @ 5V  
• Four Non-Volatile Data Registers  
The digital controlled potentiometer is implemented using  
1023 resistive elements in a series array. Between each  
element are tap points connected to the wiper terminal  
through switches. The position of the wiper on the array is  
controlled by the user through the SPI bus interface. The  
potentiometer has associated with it a volatile Wiper Counter  
Register (WCR) and four non-volatile Data Registers that  
can be directly written to and read by the user. The contents  
of the WCR controls the position of the wiper on the resistor  
array though the switches. Power-up recalls the contents of  
the default data register (DR0) to the WCR.  
• Non-Volatile Storage of Multiple Wiper Positions  
• Power-on Recall. Loads Saved Wiper Position on Power-up  
• Standby Current < 3µA Max  
• System V : 2.7V to 5.5V Operation  
CC  
• Analog V+/V-: -5V to +5V  
• 100kEnd to End Resistance  
• 100 yr. Data Retention  
The XDCP can be used as a three-terminal potentiometer or  
as a two terminal variable resistor in a wide variety of  
applications including control, parameter adjustments, and  
signal processing.  
• Endurance: 100, 000 Data Changes Per Bit Per Register  
• 14 Ld TSSOP  
• Dual Supply Version of the X9111  
• Low Power CMOS  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
Pinout  
X9110  
14 LD TSSOP  
TOP VIEW  
V+  
S0  
14  
13  
12  
11  
10  
1
2
3
4
5
6
7
V
CC  
R
R
R
L
A0  
H
W
SCK  
WP  
SI  
HOLD  
CS  
9
8
VSS  
V-  
Functional Diagram  
V
R
V+  
CC  
H
ADDRESS  
DATA  
WRITE  
READ  
POWER-ON RECALL  
100kΩ  
1024-TAPS  
POT  
STATUS  
TRANSFER  
BUS  
INTERFACE &  
CONTROL  
WIPER COUNTER  
REGISTER (WCR)  
SPI  
BUS  
WIPER  
INTERFACE  
DATA REGISTERS  
(DR0-DR3)  
CONTROL  
R
R
V-  
V
NC  
NC  
W
L
SS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
XDCP is a trademark of Intersil Americas INC. Copyright Intersil Americas Inc. 2005. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  
1

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