APPLICATION NOTE
A V A I L A B L E
AN95 • AN103 • AN107
16K/64K
MPS™ EEPROM
X84161/641
µPort Saver EEPROM
DESCRIPTION
FEATURES
• Up to 10MHz data transfer rate
• 25ns Read Access Time
• Direct interface to microprocessors and micro-
controllers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low power CMOS
—2.5V–5.5V and 5V 10% versions
—Standby current less than 1µA
—Active current less than 1mA
• Byte or page write capable
—32-byte page write mode
• Typical nonvolatile write cycle time: 2ms
• High reliability
—100,000 endurance cycles
—Guaranteed data retention: 100 years
• Small packages options
—8-lead mini-DIP package
—8-lead SOIC package
—8, 20-lead TSSOP package
The µPort Saver memories need no serial ports or
special hardware and connect to the processor mem-
ory bus. Replacing bytewide data memory, the µPort
Saver uses bytewide memory control functions, takes
a fraction of the board space and consumes much less
power. Replacing serial memories, the µPort Saver
provides all the serial benefits, such as low cost, low
power, low voltage, and small package size, while
releasing I/Os for more important uses.
The µPort Saver memory outputs data within 25ns of
an active read signal. This is less than the read access
time of most hosts and provides “no-wait-state” opera-
tion. This prevents bottlenecks on the bus. With rates
to 10MHz, the µPort Saver supplies data faster than
required by most host read cycle specifications. This
eliminates the need for software NOPs.
The µPort Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This “bit serial” interface allows
the µPort Saver to work well in 8-bit, 16-bit, 32-bit, and
64-bit systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
BLOCK DIAGRAM
Internal Block Diagram
MPS
System Connection
H.V. Generation
Timing & Control
WP
A
µP
µC
15
A
D
0
7
DSP
ASIC
RISC
CE
I/O
OE
EEPROM
Array
Command
Decode
and
Control
Logic
X
DEC
D
0
8K x 8
2K x 8
P0/CS
OE
P1/CLK
P2/DI
Ports
Saved
WE
WE
P3/DO
Y Decode
Data Register
Characteristics subject to change without notice. 1 of 17
REV 1.0 6/30/00
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