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X68C64EM

更新时间： 2024-11-19 13:15:35
品牌 Logo 应用领域
XICOR /
页数 文件大小 规格书
12页 65K
描述
EEPROM, 8KX8, 120ns, Parallel, CMOS, CQCC32,

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中文翻译

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X68C64EM 技术参数

是否Rohs认证：不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.91
Is Samacsys：N最长访问时间：120 ns
命令用户界面：NO数据轮询：NO
JESD-30 代码：R-XQCC-N32JESD-609代码：e0
内存密度：65536 bit内存集成电路类型：EEPROM
内存宽度：8端子数量：32
字数：8192 words字数代码：8000
最高工作温度：125 °C最低工作温度：-55 °C
组织：8KX8封装主体材料：CERAMIC
封装代码：QCCN封装等效代码：LCC32,.45X.55
封装形状：RECTANGULAR封装形式：CHIP CARRIER
页面大小：32 words并行/串行：PARALLEL
电源：5 V认证状态：Not Qualified
最大待机电流：0.0005 A子类别：EEPROMs
最大压摆率：0.06 mA标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD切换位：YES
Base Number Matches：1

X68C64EM 数据手册

 浏览型号X68C64EM的Datasheet PDF文件第2页浏览型号X68C64EM的Datasheet PDF文件第3页浏览型号X68C64EM的Datasheet PDF文件第4页浏览型号X68C64EM的Datasheet PDF文件第5页浏览型号X68C64EM的Datasheet PDF文件第6页浏览型号X68C64EM的Datasheet PDF文件第7页 
68XX Microcontroller Family Compatible  
64K  
X68C64  
8192 x 8 Bit  
E2 Micro-Peripheral  
FEATURES  
DESCRIPTION  
™
2
• CONCURRENT READ WRITE  
The X68C64 is an 8K x 8 E PROM fabricated with  
advanced CMOS Textured Poly Floating Gate Technol-  
ogy. The X68C64 features a Multiplexed Address and  
Data bus allowing a direct interface to a variety of  
popular single-chip microcontrollers operating in ex-  
panded multiplexed mode without the need for addi-  
tional interface circuitry.  
—Dual Plane Architecture  
—Isolates Read/Write Functions  
Between Planes  
—Allows Continuous Execution of Code  
From One Plane While Writing in  
the Other Plane  
• Multiplexed Address/Data Bus  
—Direct Interface to Popular 8-bit  
Microcontrollers, e.g., Motorola M6801/03,  
M68HC11 Family  
• High Performance CMOS  
—Fast Access Time, 120ns  
—Low Power  
TheX68C64isinternallyconfiguredastwoindependent  
4K x 8 memory arrays. This feature provides the ability  
toperformnonvolatilememoryupdatesinonearrayand  
continue operation out of code stored in the other array;  
effectively eliminating the need for an auxiliary memory  
device for code storage.  
—60mA Maximum Active  
To write to the X68C64, a three-byte command  
sequence must precede the byte(s) being written. The  
X68C64 also provides a second generation software  
data protection scheme called Block Protect. Block  
Protect can provide write lockout of the entire device or  
selected 1K blocks. There are eight 1K x 8 blocks that  
can be write protected individually in any combination  
required by the user. Block Protect, in addition to Write  
Controlinput,allowsthedifferentsegmentsofthememory  
to have varying degrees of alterability in normal system  
operation.  
—500µA Maximum Standby  
• Software Data Protection  
• Block Protect Register  
—Individually Set Write Lock Out in 1K Blocks  
• Toggle Bit Polling  
—Early End of Write Detection  
• Page Mode Write  
—Allows up to 32 Bytes to be Written in  
One Write Cycle  
• High Reliability  
—Endurance: 100,000 Write Cycles  
—Data Retention: 100 Years  
FUNCTIONAL DIAGRAM  
WC  
CE  
A12  
R/W  
CONTROL  
LOGIC  
SOFTWARE  
DATA  
PROTECT  
E
SEL  
A12  
X
L
A
T
C
H
E
S
D
E
C
O
D
E
A12  
M
1K BYTES  
1K BYTES  
1K BYTES  
1K BYTES  
1K BYTES  
1K BYTES  
1K BYTES  
1K BYTES  
A8–A11  
AS  
U
X
Y DECODE  
I/O & ADDRESS LATCHES AND BUFFERS  
A/D0–A/D7  
3868 FHD F02  
CONCURRENT READ WRITE™ is a trademark of Xicor, Inc.  
© Xicor, Inc. 1991, 1995, 1996 Patents Pending  
3868-2.6 9/16/96 T0/C0/D2 SH  
Characteristics subject to change without notice  
1
1234567...12

中文翻译

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 		E2 Micro-Peripheral
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 		E2 Micro-Peripheral
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