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X5329PZ-2.7A PDF预览

X5329PZ-2.7A

更新时间： 2024-11-26 20:22:19
品牌 Logo 应用领域
瑞萨 - RENESAS 光电二极管
页数 文件大小 规格书
21页 330K
描述
1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8, ROHS COMPLIANT, PLASTIC, DIP-8

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X5329PZ-2.7A 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：DIP包装说明：ROHS COMPLIANT, PLASTIC, DIP-8
针数：8Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.68其他特性：WATCHDOG TIMER, POWER-ON RESET CONTROL, SUPPLY VOLTAGE SUPERVISION
可调阈值：YES模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：R-PDIP-T8JESD-609代码：e3
长度：9.585 mm信道数量：1
功能数量：1端子数量：8
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：5.33 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

X5329PZ-2.7A 数据手册

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X5328, X5329  
®
(Replaces X25328, X25329)  
Data Sheet  
October 17, 2005  
FN8132.1  
DESCRIPTION  
CPU Supervisor with 32Kbit SPI EEPROM  
These devices combine three popular functions, Power-  
on Reset Control, Supply Voltage Supervision, and Block  
Lock Protect Serial EEPROM Memory in one package.  
This combination lowers system cost, reduces board  
space requirements, and increases reliability.  
FEATURES  
• Low V detection and reset assertion  
CC  
—Five standard reset threshold voltages  
—Re-program low V reset threshold voltage  
CC  
using special programming sequence  
Applying power to the device activates the power-on  
reset circuit which holds RESET/RESET active for a  
period of time. This allows the power supply and oscilla-  
tor to stabilize before the processor can execute code.  
—Reset signal valid to V = 1V  
CC  
• Long battery life with low power consumption  
—<1µA max standby current  
—<400µA max active current during read  
• 32Kbits of EEPROM  
The device’s low V  
detection circuitry protects the  
CC  
• Built-in inadvertent write protection  
—Power-up/power-down protection circuitry  
—Protect 0, 1/4, 1/2 or all of EEPROM array with  
user’s system from low voltage conditions by holding  
RESET/RESET active when V falls below a mini-  
CC  
mum V trip point. RESET/RESET remains asserted  
CC  
™
Block Lock protection  
until V  
returns to proper operating level and stabi-  
CC  
—In circuit programmable ROM mode  
• 2MHz SPI interface modes (0,0 & 1,1)  
• Minimize EEPROM programming time  
—32-byte page write mode  
lizes. Five industry standard V  
thresholds are  
TRIP  
available, however, Intersil’s unique circuits allow the  
threshold to be reprogrammed to meet custom  
requirements or to fine-tune the threshold in applica-  
tions requiring higher precision.  
—Self-timed write cycle  
—5ms write cycle time (typical)  
• 2.7V to 5.5V and 4.5V to 5.5V power supply  
operation  
• Available packages  
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP  
• Pb-free plus anneal available (RoHS compliant)  
BLOCK DIAGRAM  
WP  
Protect Logic  
SI  
Data  
Status  
Register  
Register  
SO  
Command  
Decode &  
Control  
SCK  
CS  
8Kbits  
8Kbits  
Logic  
16Kbits  
Reset  
Timebase  
RESET/RESET  
Power-on and  
Low Voltage  
Reset  
VCC  
+
-
Generation  
X5328 = RESET  
X5329 = RESET  
VTRIP  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
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