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X5323S8IZ-T

更新时间： 2024-11-08 21:07:03
品牌 Logo 应用领域
瑞萨 - RENESAS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
20页 341K
描述
IC,SERIAL EEPROM,4KX8,CMOS,SOP,8PIN,PLASTIC

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中文翻译

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X5323S8IZ-T 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred包装说明：,
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.11
JESD-609代码：e3湿度敏感等级：1
峰值回流温度（摄氏度）：225端子面层：Matte Tin (Sn) - annealed
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

X5323S8IZ-T 数据手册

 浏览型号X5323S8IZ-T的Datasheet PDF文件第2页浏览型号X5323S8IZ-T的Datasheet PDF文件第3页浏览型号X5323S8IZ-T的Datasheet PDF文件第4页浏览型号X5323S8IZ-T的Datasheet PDF文件第5页浏览型号X5323S8IZ-T的Datasheet PDF文件第6页浏览型号X5323S8IZ-T的Datasheet PDF文件第7页 
X5323, X5325  
®
(Replaces X25323, X25325)  
Data Sheet  
June 30, 2008  
FN8131.2  
CPU Supervisor with 32kBit SPI EEPROM  
Features  
These devices combine four popular functions, Power-on  
Reset Control, Watchdog Timer, Supply Voltage Supervision,  
and Block Lock Protect Serial EEPROM Memory in one  
package. This combination lowers system cost, reduces  
board space requirements, and increases reliability.  
• Selectable watchdog timer  
• Low VCC detection and reset assertion  
- Five standard reset threshold voltages  
- Re-program low VCC reset threshold voltage using  
special programming sequence  
Applying power to the device activates the power-on reset  
circuit which holds RESET/RESET active for a period of  
time. This allows the power supply and oscillator to stabilize  
before the processor can execute code.  
- Reset signal valid to VCC = 1V  
• Determine watchdog or low voltage reset with a volatile  
flag bit  
• Long battery life with low power consumption  
- <50µA max standby current, watchdog on  
- <1µA max standby current, watchdog off  
- <400µA max active current during read  
The Watchdog Timer provides an independent protection  
mechanism for microcontrollers. When the microcontroller  
fails to restart a timer within a selectable time out interval,  
the device activates the RESET/RESET signal. The user  
selects the interval from three preset values. Once selected,  
the interval does not change, even after cycling the power.  
• 32kbits of EEPROM  
• Built-in inadvertent write protection  
- Power-up/power-down protection circuitry  
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block  
Lock™ protection  
The device’s low VCC detection circuitry protects the user’s  
system from low voltage conditions, resetting the system  
when VCC falls below the minimum VCC trip point.  
RESET/RESET is asserted until VCC returns to proper  
operating level and stabilizes. Five industry standard VTRIP  
thresholds are available, however, Intersil’s unique circuits  
allow the threshold to be reprogrammed to meet custom  
requirements or to fine-tune the threshold for applications  
requiring higher precision.  
- In circuit programmable ROM mode  
• 2MHz SPI interface modes (0,0 and 1,1)  
• Minimize EEPROM programming time  
- 32-byte page write mode  
- Self-timed write cycle  
- 5ms write cycle time (typical)  
• 2.7V to 5.5V and 4.5V to 5.5V power supply  
operation  
• Available packages  
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP  
• Pb-free (RoHS compliant)  
Block Diagram  
WATCHDOG TRANSITION  
DETECTOR  
WATCHDOG  
TIMER RESET  
WP  
PROTECT LOGIC  
RESET/RESET  
X5323 = RESET  
SI  
DATA  
REGISTER  
STATUS  
REGISTER  
SO  
RESET AND  
WATCHDOG  
TIMEBASE  
COMMAND  
DECODE AND  
CONTROL  
LOGIC  
X5325 = RESET  
SCK  
8kBITS  
8kBITS  
CS/WDI  
V
THRESHOLD  
RESET LOGIC  
CC  
16kBITS  
POWER-ON AND  
LOW VOLTAGE  
RESET  
V
+
-
CC  
GENERATION  
V
TRIP  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
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