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X5169V14 PDF预览

X5169V14

更新时间: 2024-11-06 22:20:03
品牌 Logo 应用领域
英特矽尔 - INTERSIL 监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
19页 363K
描述
CPU Supervisor with 16Kbit SPI EEPROM

X5169V14 数据手册

 浏览型号X5169V14的Datasheet PDF文件第2页浏览型号X5169V14的Datasheet PDF文件第3页浏览型号X5169V14的Datasheet PDF文件第4页浏览型号X5169V14的Datasheet PDF文件第5页浏览型号X5169V14的Datasheet PDF文件第6页浏览型号X5169V14的Datasheet PDF文件第7页 
X5168, X5169  
®
(Replaces X25268, X25169)  
Data Sheet  
September 16, 2005  
FN8130.1  
CPU Supervisor with 16Kbit SPI EEPROM  
Features  
• Low VCC Detection and Reset Assertion  
- Five standard reset threshold voltages  
- Re-program low VCC reset threshold voltage using  
special programming sequence  
These devices combine three popular functions, Power-on  
Reset Control, Supply Voltage Supervision, and Block Lock  
Protect Serial EEPROM Memory in one package. This  
combination lowers system cost, reduces board space  
requirements, and increases reliability.  
- Reset signal valid to VCC = 1V  
Applying power to the device activates the power-on reset  
circuit which holds RESET/RESET active for a period of  
time. This allows the power supply and oscillator to stabilize  
before the processor can execute code.  
• Long Battery Life with Low Power Consumption  
- <50µA max standby current, watchdog on  
- <1µA max standby current, watchdog off  
- <400µA max active current during read  
The device’s low VCC detection circuitry protects the user’s  
system from low voltage conditions by holding  
• 16Kbits of EEPROM  
• Built-in Inadvertent Write Protection  
RESET/RESET active when VCC falls below a minimum VCC  
trip point. RESET/RESET remains asserted until VCC returns  
to proper operating level and stabilizes. Five industry  
standard VTRIP thresholds are available, however, Intersil’s  
unique circuits allow the threshold to be reprogrammed to  
meet custom requirements or to fine-tune the threshold in  
applications requiring higher precision.  
- Power-up/power-down protection circuitry  
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block  
Lockprotection  
- In circuit programmable ROM mode  
• 2MHz SPI Interface Modes (0,0 & 1,1)  
• Minimize EEPROM Programming Time  
- 32-byte page write mode  
- Self-timed write cycle  
- 5ms write cycle time (typical)  
• 2.7V to 5.5V and 4.5V to 5.5V Power Supply  
Operation  
• Available Packages  
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
Block Diagram  
WP  
Protect Logic  
SI  
Data  
Register  
Status  
Register  
SO  
Command  
Decode &  
Control  
SCK  
CS  
4Kbits  
4Kbits  
Logic  
8Kbits  
Reset  
Timebase  
RESET/RESET  
Power-on and  
Low Voltage  
Reset  
V
+
-
CC  
Generation  
X5168 = RESET  
X5169 = RESET  
V
TRIP  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  

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