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X5168S8Z

更新时间： 2024-09-18 21:20:27
品牌 Logo 应用领域
瑞萨 - RENESAS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
页数 文件大小 规格书
20页 857K
描述
CPU Supervisor with 16Kbit SPI EEPROM; PDIP8, SOIC8; Temp Range: See Datasheet

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中文翻译

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X5168S8Z 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：PDIP, SOIC包装说明：SOIC-8
针数：8, 8Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.31Is Samacsys：N
可调阈值：YES模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9022 mm湿度敏感等级：1
信道数量：1功能数量：1
端子数量：8最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.7272 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：3.9116 mmBase Number Matches：1

X5168S8Z 数据手册

 浏览型号X5168S8Z的Datasheet PDF文件第2页浏览型号X5168S8Z的Datasheet PDF文件第3页浏览型号X5168S8Z的Datasheet PDF文件第4页浏览型号X5168S8Z的Datasheet PDF文件第5页浏览型号X5168S8Z的Datasheet PDF文件第6页浏览型号X5168S8Z的Datasheet PDF文件第7页 
DATASHEET  
X5168, X5169 (Replaces X25268,
CPU Supervisor with 16Kbit SPI EEPROM  
FN8130  
Rev 2.00  
June 15, 2006  
These devices combine three popular functions, Power-on  
Reset Control, Supply Voltage Supervision, and Block Lock  
Protect Serial EEPROM Memory in one package. This  
combination lowers system cost, reduces board space  
requirements, and increases reliability.  
Features  
• Low VCC Detection and Reset Assertion  
- Five standard reset threshold voltages  
- Re-program low VCC reset threshold voltage using  
special programming sequence  
Applying power to the device activates the power-on reset  
circuit which holds RESET/RESET active for a period of  
time. This allows the power supply and oscillator to stabilize  
before the processor can execute code.  
- Reset signal valid to VCC = 1V  
• Long Battery Life with Low Power Consumption  
- <50µA max standby current, watchdog on  
- <1µA max standby current, watchdog off  
- <400µA max active current during read  
The device’s low VCC detection circuitry protects the user’s  
system from low voltage conditions by holding  
• 16Kbits of EEPROM  
RESET/RESET active when VCC falls below a minimum VCC  
trip point. RESET/RESET remains asserted until VCC returns  
to proper operating level and stabilizes. Five industry  
standard VTRIP thresholds are available, however, Intersil’s  
unique circuits allow the threshold to be reprogrammed to  
meet custom requirements or to fine-tune the threshold in  
applications requiring higher precision.  
• Built-in Inadvertent Write Protection  
- Power-up/power-down protection circuitry  
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block  
Lock™ protection  
- In circuit programmable ROM mode  
• 2MHz SPI Interface Modes (0,0 & 1,1)  
• Minimize EEPROM Programming Time  
- 32-byte page write mode  
- Self-timed write cycle  
- 5ms write cycle time (typical)  
• 2.7V to 5.5V and 4.5V to 5.5V Power Supply  
Operation  
• Available Packages  
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
Block Diagram  
WP  
Protect Logic  
SI  
Data  
Register  
Status  
Register  
SO  
Command  
Decode &  
Control  
SCK  
CS  
4Kbits  
4Kbits  
Logic  
8Kbits  
Reset  
Timebase  
RESET/RESET  
Power-on and  
Low Voltage  
Reset  
V
+
-
CC  
Generation  
X5168 = RESET  
X5169 = RESET  
V
TRIP  
FN8130 Rev 2.00  
June 15, 2006  
Page 1 of 20  
1234567...20

中文翻译

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