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X5001P-2.7A PDF预览

X5001P-2.7A

更新时间： 2024-01-13 17:04:45
品牌 Logo 应用领域
英特矽尔 - INTERSIL 光电二极管监控
页数 文件大小 规格书
20页 305K
描述
CPU Supervisor

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中文翻译

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X5001P-2.7A 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP-8
针数：8Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.73可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码：R-PDIP-T8
JESD-609代码：e0长度：9.525 mm
信道数量：1功能数量：1
端子数量：8最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP8,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3/5 V
认证状态：Not Qualified座面最大高度：5.334 mm
子类别：Power Management Circuits最大供电电流 (Isup)：5 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：5 V表面贴装：NO
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

X5001P-2.7A 数据手册

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X5001  
®
Data Sheet  
May 30, 2006  
FN8125.1  
DESCRIPTION  
CPU Supervisor  
This device combines three popular functions, Power-  
on Reset, Watchdog Timer, and Supply Voltage  
Supervision in one package. This combination lowers  
system cost, reduces board space requirements, and  
increases reliability.  
FEATURES  
• 200ms power-on reset delay  
• Low V detection and reset assertion  
CC  
—Five standard reset threshold voltages  
—Adjust low V reset threshold voltage using  
CC  
The watchdog timer provides an independent protec-  
tion mechanism for microcontrollers. During a system  
failure, the device will respond with a RESET signal  
after a selectable time out interval. The user selects the  
interval from three preset values. Once selected, the  
interval does not change, even after cycling the power.  
special programming sequence  
—Reset signal valid to V = 1V  
CC  
• Selectable nonvolatile watchdog timer  
—0.2, 0.6, 1.4 seconds  
—Off selection  
—Select settings through software  
• Long battery life with low power consumption  
—<50µA max standby current, watchdog on  
—<1µA max standby current, watchdog off  
• 2.7V to 5.5V operation  
The user’s system is protected from low voltage condi-  
tions by the device’s low V detection circuitry. When  
CC  
V
falls below the minimum V trip point, the system  
CC  
CC  
is reset. RESET is asserted until V returns to proper  
CC  
• SPI mode 0 interface  
operating levels and stabilizes. Five industry standard  
• Built-in inadvertent write protection  
—Power-up/power-down protection circuitry  
—Watchdog change latch  
V
thresholds are available, however, Intersil’s  
TRIP  
unique circuits allow the threshold to be reprogrammed  
to meet custom requirements or to fine-tune the thresh-  
old for applications requiring higher precision.  
• High reliability  
• Available packages  
—8 Ld TSSOP  
—8 Ld SOIC  
—8 Ld PDIP  
™
The device utilizes Intersil’s proprietary Direct Write  
cell for the watchdog timer control bits and the V  
TRIP  
storage element, providing a minimum endurance of  
100,000 write cycles and a minimum data retention of  
100 years.  
• Pb-free plus anneal available (RoHS compliant)  
BLOCK DIAGRAM  
RESET  
Watchdog  
Transition  
Detector  
Watchdog  
Timer  
SI  
Data  
Register  
Reset &  
Watchdog  
Timebase  
SO  
Command  
Decode &  
Control  
SCK  
CS/WDI  
Logic  
Power-on/  
Low Voltage  
REset  
VCC  
+
-
Generation  
V
TRIP  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
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