X40420, X40421
®
4kbit EEPROM
Data Sheet
May 25, 2006
FN8117.1
PRELIMINARY
• Monitor voltages: 5V to 1.6V
• Memory security
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
• Battery switch backup
• V
5mA to 50mA
OUT
FEATURES
APPLICATIONS
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
• Communications equipment
—Routers, hubs, switches
—Disk arrays
• Industrial systems
—Process control
—Intelligent instrumentation
• Computer systems
—Desktop computers
—Network servers
—V
programmable down to 0.9V
TRIP2
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to V = 1V
CC
—Monitor two voltages or detect power fail
• Battery switch backup
• V
V
: 5mA to 50mA from V ; or 250µA from
OUT
BATT
CC
• Fault detection register
X40420, X40421
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA typical battery current in backup mode
• 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0 or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
Standard VTRIP1 Level Standard VTRIP2 Level Suffix
4.6V (±1%)
4.6V (±1%)
2.9V(±1.7%)
2.9V(±1.7%)
2.6V (±2%)
1.6V (±3%)
-A
-B
-C
See “Ordering Information” for more details
For Custom Settings, call Intersil.
DESCRIPTION
The X40420, X40421 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary supervision, manual reset, and Block
™
Lock protect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to V
activates the power-on reset
CC
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
—14 Ld SOIC, TSSOP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
VOUT
+
-
V2FAIL
WDO
V2MON
VTRIP2
V2 Monitor
Logic
Watchdog
and
Reset Logic
Fault Detection
Register
Data
Register
SDA
WP
VOUT
Status
Register
Command
Decode Test
& Control
Logic
EEPROM
Array
MR
RESET
X40420
SCL
Power-on,
Manual Reset
Low Voltage
Reset
VOUT
RESET
X40421
+
VCC
(V1MON)
VTRIP1
Generation
VCC Monitor
Logic
-
BATT-ON
VOUT
LOWLINE
System
Battery
Switch
VBATT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
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