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X28VC256JI-90 PDF预览

X28VC256JI-90

更新时间: 2024-01-20 09:15:36
品牌 Logo 应用领域
XICOR 存储内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
24页 111K
描述
5 Volt, Byte Alterable E2PROM

X28VC256JI-90 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.89
Is Samacsys:N最长访问时间:90 ns
命令用户界面:NO数据轮询:YES
耐久性:100000 Write/Erase CyclesJESD-30 代码:R-PQCC-J32
JESD-609代码:e0内存密度:262144 bit
内存集成电路类型:EEPROM内存宽度:8
端子数量:32字数:32768 words
字数代码:32000最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX8
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC32,.5X.6封装形状:RECTANGULAR
封装形式:CHIP CARRIER页面大小:128 words
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified最大待机电流:0.025 A
子类别:EEPROMs最大压摆率:0.08 mA
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
切换位:YESBase Number Matches:1

X28VC256JI-90 数据手册

 浏览型号X28VC256JI-90的Datasheet PDF文件第2页浏览型号X28VC256JI-90的Datasheet PDF文件第3页浏览型号X28VC256JI-90的Datasheet PDF文件第4页浏览型号X28VC256JI-90的Datasheet PDF文件第5页浏览型号X28VC256JI-90的Datasheet PDF文件第6页浏览型号X28VC256JI-90的Datasheet PDF文件第7页 
256K  
X28VC256  
5 Volt, Byte Alterable E2PROM  
DESCRIPTION  
32K x 8 Bit  
FEATURES  
Access Time: 45ns  
Simple Byte and Page Write  
Single 5V Supply  
The X28VC256 is a second generation high perfor-  
mance CMOS 32K x 8 E PROM. It is fabricated with  
Xicor’s proprietary, textured poly floating gate tech-  
nology, providing a highly reliable 5 Volt only nonvolatile  
memory.  
2
No External High Voltages or V Control  
PP  
Circuits  
Self-Timed  
The X28VC256 supports a 128-byte page write opera-  
tion, effectively providing a 24µs/byte write cycle and  
enabling the entire memory to be typically rewritten in  
less than 0.8 seconds. The X28VC256 also features  
DATA Polling and Toggle Bit Polling, two methods of  
providing early end of write detection. The X28VC256  
also supports the JEDEC standard Software Data Pro-  
tection feature for protecting against inadvertent writes  
during power-up and power-down.  
No Erase Before Write  
No Complex Programming Algorithms  
—No Overerase Problem  
Low Power CMOS:  
Active: 80mA  
Standby: 10mA  
Software Data Protection  
Protects Data Against System Level  
Inadvertent Writes  
High Speed Page Write Capability  
Endurance for the X28VC256 is specified as a minimum  
100,000 write cycles per byte and an inherent data  
retention of 100 years.  
Highly Reliable Direct Write Cell  
Endurance: 100,000 Write Cycles  
Data Retention: 100 Years  
Early End of Write Detection  
DATA Polling  
Toggle Bit Polling  
PIN CONFIGURATION  
PLASTIC DIP  
CERDIP  
FLAT PACK  
LCC  
PLCC  
SOIC  
TSOP  
A14  
1
2
3
4
5
6
7
8
9
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CC  
4
3
2
1
32 31 30  
29  
A
WE  
A
A
A
I/O  
I/O  
I/O  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A
A
A
A
A
A
A
NC  
V
NC  
WE  
12  
2
1
0
0
1
2
3
4
5
6
7
12  
14  
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
A
A
A
A
A
A
A
5
6
7
8
9
A
A
A
13  
6
5
4
3
2
1
0
8
A
8
A
9
28  
27  
26  
25  
24  
23  
22  
21  
9
11  
A
NC  
OE  
A
11  
NC  
X28VC256  
OE  
V
SS  
NC  
X28VC256  
X28VC256  
9
CC  
A
10  
11  
12  
13  
10  
10  
I/O  
10  
11  
12  
13  
14  
15  
16  
3
4
5
6
7
CE  
CE  
I/O  
I/O  
I/O  
I/O  
I/O  
A
A
A
A
13  
8
9
10  
11  
12  
13  
14  
I/O  
7
I/O  
6
I/O  
5
I/0  
4
NC  
I/O  
7
I/O  
0
I/O  
1
I/O  
2
I/O  
0
6
14 15 16 17 18 19 20  
CE  
11  
A
OE  
10  
V
I/O  
3
SS  
3869 FHD F03  
3869 ILL F22  
3869 FHD F02  
©Xicor, Inc. 1991, 1995 Patents Pending  
3869-2.6 4/2/96 T4/C4/D0 NS  
Characteristics subject to change without notice  
1

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