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X28HC64JZ-70-T1 PDF预览

X28HC64JZ-70-T1

更新时间： 2024-11-06 06:09:55
品牌 Logo 应用领域
瑞萨 - RENESAS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
18页 436K
描述
EEPROM, 8KX8, 70ns, Parallel, CMOS, PQCC32

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X28HC64JZ-70-T1 数据手册

 浏览型号X28HC64JZ-70-T1的Datasheet PDF文件第2页浏览型号X28HC64JZ-70-T1的Datasheet PDF文件第3页浏览型号X28HC64JZ-70-T1的Datasheet PDF文件第4页浏览型号X28HC64JZ-70-T1的Datasheet PDF文件第5页浏览型号X28HC64JZ-70-T1的Datasheet PDF文件第6页浏览型号X28HC64JZ-70-T1的Datasheet PDF文件第7页 
DATASHEET  
64k, 8k x 8-Bit 5 Volt, Byte Alterable EEPROM  
X28HC64  
Features  
The X28HC64 is an 8k x 8 EEPROM, fabricated with Intersil’s  
proprietary, high performance, floating gate CMOS technology.  
Like all Intersil programmable nonvolatile memories, the  
X28HC64 is a 5V only device. It features the JEDEC approved  
pinout for byte-wide memories, compatible with industry  
standard RAMs.  
• 70ns access time  
• Simple byte and page write  
- Single 5V supply  
- No external high voltages or VP-P control circuits  
- Self-timed  
- No erase before write  
The X28HC64 supports a 64-byte page write operation, effectively  
providing a 32µs/byte write cycle, and enabling the entire  
memory to be typically written in 0.25 seconds. The X28HC64  
also features DATA Polling and Toggle Bit Polling, two methods  
providing early end of write detection. In addition, the X28HC64  
includes a user-optional software data protection mode that  
further enhances Intersil’s hardware write protect capability.  
- No complex programming algorithms  
- No overerase problem  
• Low power CMOS  
- 40mA active current maximum  
• 200µA standby current maximum  
• Fast write cycle times  
Intersil EEPROMs are designed and tested for applications  
requiring extended endurance. Inherent data retention is  
greater than 100 years.  
- 64-byte page write operation  
- Byte or page write cycle: 2ms typical  
- Complete memory rewrite: 0.25s typical  
- Effective byte write cycle time: 32µs typical  
• Software data protection  
• End of write detection  
- DATA polling  
- Toggle bit  
• High reliability  
- Endurance: 100,000 cycles  
- Data retention: 100 years  
• JEDEC approved byte-wide pinout  
• Pb-free available (RoHS compliant)  
Pin Configurations  
X28HC64  
(28 LD PDIP, SOIC)  
TOP VIEW  
X28HC64  
(32 LD PLCC)  
TOP VIEW  
1
2
3
4
5
6
7
8
9
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CC  
NC  
WE  
NC  
A
12  
4
3
2
1 32 31 30  
29  
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
A
A
A
A
A
A
A
5
6
7
8
9
A
8
6
5
4
3
2
1
0
A
8
28  
27  
26  
25  
24  
23  
22  
21  
A
9
A
9
A
11  
A
11  
NC  
OE  
OE  
X28HC64  
X28HC64  
A
10  
A
10  
11  
12  
13  
10  
CE  
I/O  
CE  
I/O  
10  
11  
12  
13  
14  
7
NC  
I/O  
7
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
6
5
4
3
0
1
2
I/O  
0
6
14 15 16 17 18 19 20  
I/O  
V
SS  
June 27, 2016  
FN8109.4  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2006, 2009, 2015, 2016. All Rights Reserved  
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.  
All other trademarks mentioned are the property of their respective owners.  
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