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X28HC256J-15 PDF预览

X28HC256J-15

更新时间: 2024-11-19 12:17:15
品牌 Logo 应用领域
XICOR 存储内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
24页 112K
描述
5 Volt, Byte Alterable E2PROM

X28HC256J-15 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QCCJ, LDCC32,.5X.6Reach Compliance Code:unknown
风险等级:5.61Is Samacsys:N
最长访问时间:150 ns其他特性:100000 ENDURANCE WRITE CYCLES; 100 YEARS DATA RETENTION
命令用户界面:NO数据轮询:YES
数据保留时间-最小值:100耐久性:1000000 Write/Erase Cycles
JESD-30 代码:R-PQCC-J32JESD-609代码:e0
长度:13.97 mm内存密度:262144 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:32
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC32,.5X.6
封装形状:RECTANGULAR封装形式:CHIP CARRIER
页面大小:128 words并行/串行:PARALLEL
电源:5 V编程电压:5 V
认证状态:Not Qualified座面最大高度:3.56 mm
最大待机电流:0.0005 A子类别:EEPROMs
最大压摆率:0.06 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD切换位:YES
宽度:11.43 mm最长写入周期时间 (tWC):5 ms
Base Number Matches:1

X28HC256J-15 数据手册

 浏览型号X28HC256J-15的Datasheet PDF文件第2页浏览型号X28HC256J-15的Datasheet PDF文件第3页浏览型号X28HC256J-15的Datasheet PDF文件第4页浏览型号X28HC256J-15的Datasheet PDF文件第5页浏览型号X28HC256J-15的Datasheet PDF文件第6页浏览型号X28HC256J-15的Datasheet PDF文件第7页 
256K  
X28HC256  
5 Volt, Byte Alterable E2PROM  
DESCRIPTION  
32K x 8 Bit  
FEATURES  
Access Time: 70ns  
Simple Byte and Page Write  
Single 5V Supply  
The X28HC256 is a second generation high perfor-  
mance CMOS 32K x 8 E PROM. It is fabricated with  
Xicor’s proprietary, textured poly floating gate tech-  
nology, providing a highly reliable 5 Volt only nonvolatile  
memory.  
2
No External High Voltages or V Control  
PP  
Circuits  
Self-Timed  
The X28HC256 supports a 128-byte page write opera-  
tion, effectively providing a 24µs/byte write cycle and  
enabling the entire memory to be typically rewritten in  
less than 0.8 seconds. The X28HC256 also features  
DATA Polling and Toggle Bit Polling, two methods of  
providing early end of write detection. The X28HC256  
also supports the JEDEC standard Software Data Pro-  
tection feature for protecting against inadvertent writes  
during power-up and power-down.  
No Erase Before Write  
No Complex Programming Algorithms  
—No Overerase Problem  
Low Power CMOS:  
Active: 60mA  
Standby: 500µA  
Software Data Protection  
Protects Data Against System Level  
Inadvertent Writes  
High Speed Page Write Capability  
EndurancefortheX28HC256isspecifiedasaminimum  
100,000 write cycles per byte and an inherent data  
retention of 100 years.  
Highly Reliable Direct Write Cell  
Endurance: 100,000 Write Cycles  
Data Retention: 100 Years  
Early End of Write Detection  
DATA Polling  
Toggle Bit Polling  
PIN CONFIGURATION  
PLASTIC DIP  
CERDIP  
FLAT PACK  
SOIC  
LCC  
PLCC  
A14  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CC  
TSOP  
A
2
3
4
5
6
7
8
9
WE  
12  
4
3
2
1
32 31 30  
A
A
A
I/O  
I/O  
I/O  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A
A
A
A
A
A
A
NC  
V
NC  
WE  
2
1
0
0
1
2
3
4
5
6
7
12  
14  
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
13  
A
A
A
A
A
A
A
5
6
7
8
9
29  
28  
27  
26  
25  
24  
23  
22  
21  
A
A
A
6
5
4
3
2
1
0
8
A
8
A
9
9
11  
A
11  
NC  
OE  
A
NC  
OE  
X28HC256  
X28HC256  
V
SS  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
X28HC256  
A
10  
9
CC  
10  
11  
12  
13  
10  
10  
11  
12  
13  
14  
15  
16  
CE  
3
4
5
6
7
CE  
10  
11  
12  
13  
14  
I/O  
7
I/O  
6
I/O  
5
I/0  
4
A
A
A
A
13  
8
9
NC  
I/O  
I/O  
7
I/O  
0
I/O  
1
I/O  
2
I/O  
0
6
14 15 16 17 18 19 20  
CE  
11  
A
OE  
10  
V
I/O  
3
SS  
3859 ILL F22  
3859 FHD F03  
3859 FHD F02  
©Xicor, Inc. 1991, 1995 Patents Pending  
3859-2.8 8/5/97 T1/C0/D0 EW  
Characteristics subject to change without notice  
1

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