APPLICATION NOTE
A V A I L A B L
AN61
Preliminary Information
Recommended System Management
Alternative: X5563
E
128K
16K x 8 Bit
X25128
SPI Serial EEPROM with Block Lock™ Protection
FEATURES
DESCRIPTION
• 2MHz clock rate
• SPI modes (0,0 & 1,1)
• 16K X 8 bits
—32-byte page mode
• Low Power CMOS
—<1µA standby current
—<5mA active current
• 2.7V To 5.5V power supply
• Block lock protection
—Protect 1/4, 1/2 or all of EEPROM array
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Write enable latch
The X25128 is a CMOS 131,072-bit serial EEPROM,
internally organized as 16K x 8. The X25128 features
a Serial Peripheral Interface (SPI) and software proto-
col, allowing operation on a simple three-wire bus. The
bus signals are a clock input (SCK) plus separate data
in (SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X25128 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25128 will ignore transitions on
its inputs, thus allowing the host to service higher pri-
ority interrupts. The WP input can be used as a hard-
wire input to the X25128 disabling all write attempts to
the status register, thus providing a mechanism for lim-
iting end user capability of altering 0, 1/4, 1/2 or all of
the memory.
—Write protect pin
• Self-timed write cycle
—5ms write cycle time (typical)
• High reliability
—Endurance: 1 million cycles
—Data retention: 100 years
—ESD protection: 2000V on all pins
• Packages
The X25128 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
—8-Lead XBGA
—14-lead SOIC
BLOCK DIAGRAM
Write
Protect
Logic
Status
Register
X Decode
Logic
16K Byte
Array
128
128
256
16 X 256
16 X 256
32 X 256
SO
Command
Decode
and
Control
Logic
SI
SCK
CS
HOLD
Write
Control
and
Timing
Logic
32
8
WP
Y Decode
Data Register
Characteristics subject to change without notice. 1 of 14
REV 1.1 9/8/00
www.xicor.com