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X24C16PMB-3.5 PDF预览

X24C16PMB-3.5

更新时间: 2024-11-20 22:49:19
品牌 Logo 应用领域
XICOR 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
15页 65K
描述
Serial E2PROM

X24C16PMB-3.5 技术参数

生命周期:Obsolete包装说明:PLASTIC, DIP-8
Reach Compliance Code:unknown风险等级:5.75
Is Samacsys:N最大时钟频率 (fCLK):0.1 MHz
JESD-30 代码:R-PDIP-T8长度:10.03 mm
内存密度:16384 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:8字数:2048 words
字数代码:2000工作模式:SYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:2KX8封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
认证状态:Not Qualified座面最大高度:4.32 mm
串行总线类型:I2C最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mm最长写入周期时间 (tWC):10 ms
Base Number Matches:1

X24C16PMB-3.5 数据手册

 浏览型号X24C16PMB-3.5的Datasheet PDF文件第2页浏览型号X24C16PMB-3.5的Datasheet PDF文件第3页浏览型号X24C16PMB-3.5的Datasheet PDF文件第4页浏览型号X24C16PMB-3.5的Datasheet PDF文件第5页浏览型号X24C16PMB-3.5的Datasheet PDF文件第6页浏览型号X24C16PMB-3.5的Datasheet PDF文件第7页 
Preliminary Information  
16K  
X24C16  
2048 x 8 Bit  
Serial E2PROM  
FEATURES  
DESCRIPTION  
2
2.7V to 5.5V Power Supply  
Low Power CMOS  
—Active Read Current Less Than 1 mA  
—Active Write Current Less Than 3 mA  
—Standby Current Less Than 50 µA  
Internally Organized 2048 x 8  
2 Wire Serial Interface  
The X24C16 is a CMOS 16,384 bit serial E PROM,  
internally organized 2048 X 8. The X24C16 features a  
serialinterfaceandsoftwareprotocolallowingoperation  
on a simple two wire bus.  
The X24C16 is fabricated with Xicor’s advanced CMOS  
Textured Poly Floating Gate Technology.  
—Bidirectional Data Transfer Protocol  
Sixteen Byte Page Write Mode  
—Minimizes Total Write Time Per Byte  
Self Timed Write Cycle  
TM  
The X24C16 utilizes Xicor’s proprietary Direct Write  
cell providing a minimum endurance of 100,000 cycles  
and a minimum data retention of 100 years.  
—Typical Write Cycle Time of 5 ms  
High Reliability  
—Endurance: 100,000 Cycles  
—Data Retention: 100 Years  
8 Pin Mini-DIP, 8 Pin SOIC and 14 Pin SOIC  
Packages  
FUNCTIONAL DIAGRAM  
(8) V  
(4) V  
CC  
SS  
(7) TEST  
H.V. GENERATION  
START CYCLE  
TIMING  
& CONTROL  
START  
STOP  
(5) SDA  
LOGIC  
CONTROL  
LOGIC  
SLAVE ADDRESS  
REGISTER  
+COMPARATOR  
2
E PROM  
XDEC  
128 X 128  
LOAD  
INC  
(6) SCL  
(3) A  
2
WORD  
ADDRESS  
COUNTER  
(2) A  
(1) A  
1
0
R/W  
YDEC  
8
CK  
D
OUT  
PIN  
DATA REGISTER  
D
OUT  
ACK  
3840 FHD F01  
© Xicor, 1991 Patents Pending  
3840-1.1 7/29/96 T1/C0/D0 SH  
Characteristics subject to change without notice  
1

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