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X24C00SI-2.7 PDF预览

X24C00SI-2.7

更新时间: 2024-09-30 22:35:27
品牌 Logo 应用领域
XICOR 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
11页 46K
描述
Serial E2PROM

X24C00SI-2.7 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, SOIC-8Reach Compliance Code:unknown
风险等级:5.88Is Samacsys:N
其他特性:2 WIRE SERIAL INTERFACE最大时钟频率 (fCLK):1 MHz
数据保留时间-最小值:100耐久性:100000 Write/Erase Cycles
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm内存密度:128 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:8
字数:16 words字数代码:16
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:16X8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:SERIAL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/5 V认证状态:Not Qualified
座面最大高度:1.75 mm串行总线类型:I2C
最大待机电流:0.00005 A子类别:EEPROMs
最大压摆率:0.003 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mm最长写入周期时间 (tWC):5 ms
Base Number Matches:1

X24C00SI-2.7 数据手册

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APPLICATION NOTES  
A V A I L A B L E  
AN4 • AN12 • AN22 • AN26 • AN32  
128 Bit  
X24C00  
16 x 8 Bit  
Serial E2PROM  
FEATURES  
DESCRIPTION  
2
2.7V to 5.5V Power Supply  
The X24C00 is a CMOS 128 bit serial E PROM, inter-  
nally organized as 16 x 8. The X24C00 features a serial  
interface and software protocol allowing operation on a  
simple two wire bus.  
2
128 Bit Serial E PROM  
Low Power CMOS  
—Active Current Less Than 3mA  
—Standby Current Less Than 50µA  
Internally Organized 16 x 8  
2 Wire Serial Interface  
—Bidirectional Data Transfer Protocol  
Byte Mode Write  
2
Xicor E PROMs are designed and tested for applica-  
tions requiring extended endurance. Inherent data re-  
tention is greater than 100 years.  
The X24C00 is fabricated with Xicor’s Advanced CMOS  
Floating Gate technology.  
Self Timed Write Cycle  
—Typical Write Cycle Time of 5ms  
Push/Pull Output  
High Reliability  
—Endurance: 100,000 Cycles  
—Data Retention: 100 Years  
Available Packages  
—8-Lead MSOP  
—8-Lead PDIP  
—8-Lead SOIC  
FUNCTIONAL DIAGRAM  
PIN CONFIGURATION  
MSOP/DIP/SOIC  
CONTROL  
LOGIC  
COMMAND/ADDRESS  
SCL  
SDA  
1
2
3
4
8
7
6
5
V
REGISTER  
NC  
NC  
CC  
NC  
X24C00  
NC  
SCL  
SDA  
V
SS  
INPUT/  
OUTPUT  
BUFFER  
SHIFT REGISTER  
3836 FHD F02.1  
MEMORY ARRAY  
3836 FHD F01  
© Xicor, Inc. 1991, 1995, 1996 Patents Pending  
3836-1.5 6/10/96 T2/C1/D0 NS  
Characteristics subject to change without notice  
1

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