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X24640V20I-2.5 PDF预览

X24640V20I-2.5

更新时间: 2024-02-16 19:44:11
品牌 Logo 应用领域
XICOR 存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
17页 87K
描述
400KHz 2-Wire Serial E 2 PROM with Block Lock

X24640V20I-2.5 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, TSSOP-20Reach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
最大时钟频率 (fCLK):0.4 MHz数据保留时间-最小值:100
耐久性:100000 Write/Erase CyclesI2C控制字节:1010DDDR
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5 mm内存密度:65536 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:20
字数:8192 words字数代码:8000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8KX8
输出特性:OPEN-DRAIN封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:SERIAL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/5 V认证状态:Not Qualified
座面最大高度:1.2 mm串行总线类型:I2C
最大待机电流:0.000001 A子类别:EEPROMs
最大压摆率:0.003 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm最长写入周期时间 (tWC):10 ms
写保护:HARDWARE/SOFTWAREBase Number Matches:1

X24640V20I-2.5 数据手册

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64K  
8K x 8 Bit  
X24640  
400KHz 2-Wire Serial E2PROM with Block LockTM  
FEATURES  
DESCRIPTION  
2
Save Critical Data with Programmable  
Block Lock Protection  
—Block Lock (0, 1/4, 1/2, or all of E PROM Array)  
The X24640 is a CMOS Serial E PROM, internally  
organized 8K x 8. The device features a serial inter-  
face and software protocol allowing operation on a  
simple two wire bus. The bus operates at 400 KHz all  
the way down to 1.8V.  
2
—Software Program Protection  
—Programmable Hardware Write Protect  
In Circuit Programmable ROM Mode  
400KHz 2-Wire Serial Interfac  
—Schmitt Trigger Input Noise Suppression  
—Output Slope Control for Ground Bounce  
Noise Elimination  
Longer Battery Life With Lower Power  
—Active Read Current Less Than 1mA  
—Active Program Current Less Than 3mA  
—Standby Current Less Than 1µA  
1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V  
Power Supply Versions  
Three device select inputs (S –S ) allow up to eight  
devices to share a common two wire bus.  
0
2
A Write Protect Register at the highest address loca-  
tion, FFFFh, provides three write protection features:  
Software Write Protect, Block Lock Protect, and  
Programmable Hardware Write Protect. The Software  
Write Protect feature prevents any nonvolatile writes to  
the device until the WEL bit in the Write Protect  
Register is set. The Block Lock Protection feature  
gives the user four array block protect options, set by  
programming two bits in the Write Protect Register.  
The Programmable Hardware Write Protect feature  
allows the user to install the device with WP tied to  
32 Word Page Write Mode  
—Minimizes Total Write Time Per Word  
Internally Organized 8K x 8  
Bidirectional Data Transfer Protocol  
Self-Timed Write Cycle  
V
, program and Block Lock the desired portions of  
CC  
the memory array in circuit, and then enable the In  
Circuit Programmable ROM Mode by programming the  
WPEN bit in the Write Protect Register. After this, the  
Block Locked portions of the array, including the Write  
Protect Register itself, are permanently protected from  
being erased.  
—Typical Write Cycle Time of 5ms  
High Reliability  
—Endurance: 100,000 Cycles  
—Data Retention: 100Years  
8-Lead SOIC  
20-Lead TSSOP  
8-Lead PDIP  
FUNCTIONAL DIAGRAM  
DATA REGISTER  
Y DECODE LOGIC  
SERIAL E2PROM DATA  
AND ADDRESS (SDA)  
COMMAND  
DECODE  
AND  
CONTROL  
LOGIC  
SERIAL E2PROM  
SCL  
ARRAY  
PAGE  
8K x 8  
DECODE  
LOGIC  
2K x 8  
BLOCK LOCK AND  
WRITE PROTECT  
CONTROL LOGIC  
2K x 8  
4K x 8  
S2  
DEVICE  
SELECT  
LOGIC  
WRITE  
PROTECT  
REGISTER  
S1  
S0  
WRITE VOLTAGE  
CONTROL  
WP  
7038 FM 01  
Xicor, 1995, 1996 Patents Pending  
7038-1.2 4/25/97 T0/C2/D0 SH  
Characteristics subject to change without notice  
1

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