Preliminary Information
32K
4096 x 8 Bit
X24325
2
Advanced 2-Wire Serial E PROM with Block LockTM Protection
FEATURES
DESCRIPTION
2
• 2.7V to 5.5V Power Supply
The X24325 is a CMOS 32,768 bit serial E PROM,
internally organized 4096 x 8. The X24325 features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus.
• Low Power CMOS
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1µA
• Internally Organized 4096 x 8
• New Programmable Block Lock Protection
—Software Write Protection
Three device select inputs (S , S , S ) allow up to
eight devices to share a common two wire bus.
0
1
2
A Write Protect Register at the highest address loca-
tion, FFFh, provides three new write protection
features: Software Write Protect, Block Write Protect,
and Hardware Write Protect. The Software Write
Protect feature prevents any nonvolatile writes to the
X24325 until the WEL bit in the write protect register is
set. The Block Write Protection feature allows the user
to individually write protect four blocks of the array by
programming two bits in the write protect register. The
Programmable Hardware Write Protect feature allows
—Programmable hardware Write Protect
2
• Block Lock (0, 1/4, 1/2, or all of the E PROM
array)
• 2 Wire Serial Interface
• Bidirectional Data Transfer Protocol
• 32 Byte Page Write Mode
—Minimizes Total Write Time Per Byte
• Self Timed Write Cycle
—Typical Write Cycle Time of 5ms
• High Reliability
the user to install the X24325 with WP tied to V
,
CC
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
• Available Packages
program the entire memory array in place, and then
enable the hardware write protection by programming
a WPEN bit in the write protect register. After this,
selected blocks of the array, including the write protect
register itself, are permanently write protected.
—8-Lead PDIP
—8-Lead SOIC (JEDEC)
—14-Lead TSSOP
2
Xicor E PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
FUNCTIONAL DIAGRAM
WP
H.V. GENERATION
START CYCLE
TIMING &
CONTROL
V
V
CC
SS
WRITE PROTECT
REGISTER AND
LOGIC
START
STOP
SDA
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
+COMPARATOR
2
E PROM
128 X 256
XDEC
LOAD
WORD
INC
SCL
S
0
S
1
S
2
ADDRESS
COUNTER
R/W
YDEC
8
CK
D
OUT
PIN
DATA REGISTER
D
OUT
ACK
6552 ILL F01.1
Xicor, 1995, 1996 Patents Pending
6552-2.4 5/13/96 T1/C10/D0 NS
Characteristics subject to change without notice
1