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X24128P PDF预览

X24128P

更新时间： 2024-10-31 22:35:27
品牌 Logo 应用领域
XICOR 存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
17页 89K
描述
400KHz 2-Wire Serial E2PROM with Block Lock

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中文翻译

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X24128P 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：PLASTIC, DIP-8Reach Compliance Code：unknown
风险等级：5.91Is Samacsys：N
其他特性：100000 ENDURANCE CYCLES; 100 YEARS DATA RETENTION最大时钟频率 (fCLK)：0.4 MHz
数据保留时间-最小值：100耐久性：100000 Write/Erase Cycles
I2C控制字节：1010DDDRJESD-30 代码：R-PDIP-T8
JESD-609代码：e0长度：10.03 mm
内存密度：131072 bit内存集成电路类型：EEPROM
内存宽度：8功能数量：1
端子数量：8字数：16384 words
字数代码：16000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：16KX8输出特性：OPEN-DRAIN
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP8,.3封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：SERIAL
电源：5 V认证状态：Not Qualified
座面最大高度：4.32 mm串行总线类型：I2C
最大待机电流：0.000001 A子类别：EEPROMs
最大压摆率：0.003 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
最长写入周期时间 (tWC)：10 ms写保护：HARDWARE/SOFTWARE
Base Number Matches：1

X24128P 数据手册

 浏览型号X24128P的Datasheet PDF文件第2页浏览型号X24128P的Datasheet PDF文件第3页浏览型号X24128P的Datasheet PDF文件第4页浏览型号X24128P的Datasheet PDF文件第5页浏览型号X24128P的Datasheet PDF文件第6页浏览型号X24128P的Datasheet PDF文件第7页 
128K  
16K x 8 Bit  
X24128  
400KHz 2-Wire Serial E2PROM with Block LockTM  
FEATURES  
DESCRIPTION  
2
• Save Critical Data with Programmable  
Block Lock Protection  
—Block Lock (0, 1/4, 1/2, or all of E PROM Array)  
The X24128 is a CMOS Serial E PROM, internally  
organized 16K x 8. The device features a serial inter-  
face and software protocol allowing operation on a  
simple two wire bus.  
2
—Software Write Protection  
—Programmable Hardware Write Protect  
• In Circuit Programmable ROM Mode  
• 400KHz 2-Wire Serial Interface  
—Schmitt Trigger Input Noise Suppression  
—Output Slope Control for Ground Bounce  
Noise Elimination  
• Longer Battery Life With Lower Power  
—Active Read Current Less Than 1mA  
—Active Write Current Less Than 3mA  
—Standby Current Less Than 1µA  
• 1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V  
Power Supply Versions  
Three device select inputs (S –S ) allow up to eight  
devices to share a common two wire bus.  
0
2
A Write Protect Register at the highest address loca-  
tion, FFFFh, provides three write protection features:  
Software Write Protect, Block Lock Protect, and  
Programmable Hardware Write Protect. The Software  
Write Protect feature prevents any nonvolatile writes to  
the device until the WEL bit in the Write Protect  
Register is set. The Block Lock Protection feature  
gives the user four array block protect options, set by  
programming two bits in the Write Protect Register.  
The Programmable Hardware Write Protect feature  
allows the user to install the device with WP tied to  
• 32 Word Page Write Mode  
—Minimizes Total Write Time Per Word  
• Internally Organized 16K x 8  
• Bidirectional Data Transfer Protocol  
• Self-Timed Write Cycle  
V
, write to and Block Lock the desired portions of  
CC  
the memory array in circuit, and then enable the In  
Circuit Programmable ROM Mode by programming the  
WPEN bit HIGH in the Write Protect Register. After  
this, the Block Locked portions of the array, including  
the Write Protect Register itself, are permanently  
protected from being erased.  
—Typical Write Cycle Time of 5ms  
• High Reliability  
—Endurance: 100,000 Cycles  
—Data Retention: 100Years  
• 14-Lead SOIC  
• 16-Lead SOIC  
• 8-Lead PDIP  
FUNCTIONAL DIAGRAM  
DATA REGISTER  
Y DECODE LOGIC  
SERIAL E2PROM DATA  
AND ADDRESS (SDA)  
COMMAND  
DECODE  
AND  
CONTROL  
LOGIC  
SERIAL E2PROM  
SCL  
ARRAY  
PAGE  
16K x 8  
DECODE  
LOGIC  
4K x 8  
BLOCK LOCK AND  
WRITE PROTECT  
CONTROL LOGIC  
4K x 8  
8K x 8  
S2  
DEVICE  
SELECT  
LOGIC  
WRITE  
PROTECT  
REGISTER  
S1  
S0  
WRITE VOLTAGE  
CONTROL  
WP  
7027 FM 01  
Xicor, 1995, 1996 Patents Pending  
7027-1.3 5/14/97 T2/C0/D2 SH  
Characteristics subject to change without notice  
1
1234567...17

中文翻译

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