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X20C17SM-55 PDF预览

X20C17SM-55

更新时间: 2024-09-25 20:03:27
品牌 Logo 应用领域
XICOR 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
12页 178K
描述
Non-Volatile SRAM, 2KX8, 55ns, CMOS, PDSO28, PLASTIC, SOIC-28

X20C17SM-55 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, SOIC-28Reach Compliance Code:unknown
风险等级:5.92最长访问时间:55 ns
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:17.9 mm内存密度:16384 bit
内存集成电路类型:NON-VOLATILE SRAM内存宽度:8
功能数量:1端子数量:28
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:2KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP28,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:2.65 mm
最大待机电流:0.00025 A子类别:SRAMs
最大压摆率:0.1 mA最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

X20C17SM-55 数据手册

 浏览型号X20C17SM-55的Datasheet PDF文件第2页浏览型号X20C17SM-55的Datasheet PDF文件第3页浏览型号X20C17SM-55的Datasheet PDF文件第4页浏览型号X20C17SM-55的Datasheet PDF文件第5页浏览型号X20C17SM-55的Datasheet PDF文件第6页浏览型号X20C17SM-55的Datasheet PDF文件第7页 
APPLICATION NOTE  
A V A I L A B L E  
AN56  
16K  
2K x 8 Bit  
X20C17  
High Speed AUTOSTORENOVRAM  
DESCRIPTION  
FEATURES  
• 24-Pin Standard SRAM DIP Pinout  
• 28-Pin SOIC  
• Fast Access Time: 35ns, 45ns, 55ns  
• High Reliability  
—Endurance: 1,000,000 Nonvolatile Store  
Operations  
The Xicor X20C17 is a 2K x 8 NOVRAM featuring a  
high-speed static RAM overlaid bit-for-bit with a non-  
volatile electrically erasable PROM (E2PROM) and the  
AUTO-STORE feature which automatically saves the  
RAM contents to E2PROM at power-down. The  
X20C17 is fabricated with advanced CMOS floating  
gate technology to achieve high speed with low power  
and wide power-supply margin. The X20C17 features  
a compatible JEDEC approved byte-wide memory  
pinout for industry standard SRAMs.  
—Retention: 100Years Minimum  
• AUTOSTORE™ NOVRAM  
Automatically stores SRAM data into the  
E2PROM array when V low threshold is  
CC  
detected  
The NOVRAM design allows data to be easily trans-  
ferred from RAM to E2PROM (store) and E2PROM to  
RAM (recall). The store operation is completed in  
2.5ms or less. An automatic array recall operation  
reloads the contents of the E2PROM into RAM upon  
power-up.  
E2PROM data automatically recalled into RAM  
upon power-up  
• Low Power CMOS  
—Standby: 250µA  
• Infinite E2PROM array recall, and RAM read and  
write cycles  
Xicor NOVRAMS are designed for unlimited write  
?operations to RAM, either from the host or recalls  
from E2PROM, and a minimum 1,000,000 store opera-  
tions to the E2PROM. Data retention is specified to be  
greater than 100 years.  
BLOCK DIAGRAM  
V
Sense  
CC  
EEPROM Array  
High Speed  
Row  
Select  
A -A  
2K x 8  
SRAM  
Array  
3
8
CE  
OE  
WE  
Control  
Logic  
Column  
Select  
&
A -A  
0
2
I/OS  
A -A  
9
10  
I/O -I/O  
0
7
Xicor, Inc. 2000 Patents Pending  
2015-2.5 10/27/00 EP  
Characteristics subject to change without notice. 1 of 12  

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