Datasheet > X17256128DD8B

X17256128DD8B

更新时间： 2022-11-25 17:40:29

品牌	Logo	应用领域
赛灵思 - XILINX		可编程只读存储器
页数	文件大小	规格书
10页	103K
描述
QPRO Family of XC1700D QML Configuration PROMs

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X17256128DD8B 数据手册

QPRO Family of XC1700D QML

Configuration PROMs

DS070 (v2.1) June 1, 2000

Product Specification

Features

Description

The XC1700D QPRO™ family of configuration PROMs pro-

vide an easy-to-use, cost-effective method for storing Xilinx

FPGA configuration bitstreams.

•

Certified to MIL-PRF-38535 Appendix A QML

(Qualified Manufacturer Listing.)

Also available under the following Standard Microcircuit

Drawings (SMD): 5962-94717 and 5962-95617.

Configuration one-time programmable (OTP) read-only

memory designed to store configuration bitstreams of

Xilinx FPGA devices

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after the rising clock edge, data appears on the PROM

DATA output pin that is connected to the FPGA D pin. The

•

On-chip address counter, incremented by each rising

edge on the clock input

Simple interface to the FPGA requires only one user

I/O pin

FPGA generates the appropriate number of clock pulses to

complete the configuration. Once configured, it disables the

PROM. When the FPGA is in Slave Serial mode, the PROM

and the FPGA must both be clocked by an incoming signal.

•

Cascadable for storing longer or multiple bitstreams

Programmable reset polarity (active High or active

Low) for compatibility with different FPGA solutions

Low-power CMOS EPROM process

Available in 5V version only

Programming support by leading programmer

manufacturers.

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family.

•

For device programming, either the Xilinx Alliance™ or the

Foundation™ series development systems compiles the

FPGA design file into a standard HEX format which is then

transferred to most commercial PROM programmers.

•

Design support using the Xilinx Alliance and

Foundation series software packages.

GND

RESET/

CEO

OE/

RESET

Address Counter

CLK

EPROM

Cell

Output

DATA

Matrix

DS027_01_021500

Figure 1: Simplified Block Diagram (does not show programming circuit)

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS070 (v2.1) June 1, 2000

www.xilinx.com

Product Specification

1-800-255-7778

12 3 4 5 6 7...10

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