Preliminary Information
256K
2-Wire™ RTC
X1287
Real Time Clock/Calendar/CPU Supervisor with EEPROM
FEATURES
DESCRIPTION
• Selectable Watchdog Timer (0.25,s 0.75s, 1.75s, off)
• Power On Reset (250ms)
• Low Voltage Reset
The X1287 is a Real Time Clock with clock/calendar
CPU Supervisor circuits and two polled alarms. The dual
port clock and alarm registers allow the clock to oper-
ate, without loss of accuracy, even during read and
write operations.
• 2 Polled Alarms
—Settable on the Second, 10s of Seconds,
Minute, 10s of Minutes, Hour, Day, Month, or
Day of the Week
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
• 2 Wire Interface interoperable with I2C.
—400kHz data transfer rate
• Secondary Power Supply Input with internal
switch-over circuitry.
• Year 2000 Compliant RTC
• 32K x 8 Bits of EEPROM
—64 Byte Page Write Mode
—3 bit Block Lock
• Low Power CMOS
—<1µA Operating Current
—<3mA Active Current - EEPROM Program
—<400µA Active Current - EEPROM Read
• Single Byte Write Capability
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Package Options
The X1287 provides a watchdog timer with 3 selectable
timeout periods and off. The watchdog activates a
RESET pin when it expires. The reset also goes active
when Vcc drops below a fixed trip point. There are two
alarms where a match is monitored by polling status bits.
The device offers a backup power input pin. This Vback
pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational from
1.8 to 6 volts.
The X1287 provides a 256K bits EEPROM array, giv-
ing a safe, secure memory for critical user and configura-
tion data. This memory is unaffected by complete
failure of the main and backup supplies.
—14-Lead SOIC, 14-Lead TSSOP
BLOCK DIAGRAM
X1
Timer
Calendar
Logic
Frequency
Divider
1Hz
Time
Keeping
Registers
32.768kHz
Oscillator
X2
(SRAM)
Serial
Interface
Decoder
Control/
Status
Control
Decode
Logic
Compare
Registers
Registers
SCL
SDA
Alarm
(EEPROM)
(SRAM)
Alarm Regs
(EEPROM)
8
256K
EEPROM
ARRAY
Watchdog
Timer
Low Voltage
Reset
RESET
Xicor, Inc. 2000 Patents Pending
9900-3021.1 3/28/01 EP
Characteristics subject to change without notice. 1 of 26