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WM8144-10 PDF预览

WM8144-10

更新时间: 2024-09-25 12:19:39
品牌 Logo 应用领域
欧胜 - WOLFSON /
页数 文件大小 规格书
27页 396K
描述
Integrated 10-bit Data Acquisition system for Imaging Applications

WM8144-10 数据手册

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WM8144-10  
Production Data  
October 1997 Rev. 3.0  
Integrated 10-bit Data Acquisition system for  
Imaging Applications  
Description  
Features  
WM8144-10 integrates the analogue signal conditioning  
required by CCD sensors with a 10-bit ADC and optional  
pixel-by-pixel image compensation. WM8144-10 requires  
minimal external circuitry and provides a cost effective  
sensor-to-digital domain system solution.  
Reset level clamp  
Correlated Double Sampling (CDS)  
Fine offset level shifting  
Programmable Gain Amplification  
10-Bit ADC with maximum 6 MSPS  
Digital post-processing for pixel-by-pixel  
image compensation  
Each analogue conditioning channel provides reset level  
clamp, CDS, fine offset level shifting and gain  
amplification. The three channels are multiplexed into the  
ADC. Output from the ADC can either be direct or passed  
through a digital post-processing function. The post-  
processing provides compensation for variations in offset  
and shading on a pixel-by-pixel basis.  
Simple clocking scheme  
Control by serial or parallel interface  
Time-multiplexed eight-bit data output mode  
48 pin TQFP package  
Pin compatible with WM8144-12  
The flexible output architecture allows ten-bit data to be  
accessed either on a ten-bit bus or via a time-multiplexed  
eight-bit bus. The WM8144-10 can be configured for pixel-  
by-pixel or line-by-line multiplexing operation. Reset level  
clamp and/or CDS features can be optionally bypassed.  
Device configuration is either by a simple serial or eight-  
bit parallel interface.  
Applications  
Document scanners  
CCD sensor interfaces  
Contact image sensor (CIS) interfaces  
Block Diagram  
RLC  
VSMP MCLK  
VRLC  
VRU  
VRT  
VRB  
VRL  
VMID  
AVDD  
AGND  
DVDD1 DVDD2 DGND  
MUX  
CC[2:0]  
DV  
TIMING CONTROL  
VMID  
CL RS  
VS  
OFFSET  
S/H  
S/H  
S/H  
RINP  
GINP  
BINP  
EXTERNAL  
DATA STORE  
INTERFACE  
PGA  
CDATA(7:0)  
S/H  
WM8144-10  
CDS  
5-BIT REG  
8-BIT + SIGN  
DAC  
VMID  
ORNG  
OEB  
OFFSET  
10/8  
MUX  
IMAGE  
COMPENSATION  
PROCESSING  
M
U
X
10 BIT  
ADC  
OP[9:0]  
PGA  
S/H  
CDS  
5-BIT REG  
8-BIT + SIGN  
DAC  
VMID  
OFFSET  
PNS  
PGA  
S/H  
CONFIGURABLE  
SDI / DNA  
SCK / RNW  
SERIAL/PARALLEL  
CONTROL INTERFACE  
CDS  
5-BIT REG  
8-BIT + SIGN  
DAC  
VMID  
SEN / STB  
NRESET  
© 1997 Wolfson Microelectronics  
Production Data data sheets contain fi-  
nal specifications current on publication  
date. Supply of products conforms to  
Wolfson Microelectronics standard terms  
and conditions  
Wolfson Microelectronics  
Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK  
Tel: +44 (0) 131 667 9386  
email: admin@wolfson.co.uk  
www: http://www.wolfson.co.uk  
Fax: +44 (0) 131 667 5176  

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