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WF4M32-120G2TE5A PDF预览

WF4M32-120G2TE5A

更新时间: 2024-09-10 08:20:07
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WEDC /
页数 文件大小 规格书
15页 258K
描述
Flash Module, 4MX32, 120ns, CQFP68, 22.40 X 22.40 MM, 4.57 MM HEIGHT, HERMETICALLY SEALED, CERAMIC, QFP-68

WF4M32-120G2TE5A 数据手册

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WF4M32-XXX5  
White Electronic Designs  
PRELIMINARY*  
4MX32 5V FLASH MODULE  
FEATURES  
!
!
Organized as 4Mx32  
!
Access Times of 100, 120, 150ns  
User configurable as 8Mx16 or 16Mx8 in HIP and  
G4T packages.  
!
Packaging:  
!
Commercial, Industrial, and Extended  
Temperature Ranges  
• 66 pin, PGA Type, 1.385" square, Hermetic  
Ceramic HIP (Package 402).  
• 68 lead, 40mm Low Profile CQFP ( Package  
502 ), 3.5mm (0.140") height.  
!
!
!
5 Volt Read and Write. 5V ± 10% Supply.  
Low Power CMOS  
• 68 lead, Hermetic CQFP (G2T), 22.4mm  
(0.880") square (Package 509) 4.57mm  
(0.180") height. Designed to fit JEDEC 68  
lead 0.990CQFJ footprint (Fig. 3)  
Data Polling and Toggle Bit feature for detection  
of program or erase cycle completion.  
!
!
!
Supports reading or programming data to a  
sector not being erased.  
!
!
Sector Architecture  
RESET pin resets internal state machine to the  
read mode.  
• 32 equal size sectors of 64KBytes per each  
2Mx8 chip  
Built-in Decoupling Caps and Multiple Ground  
Pins for Low Noise Operation, Separate Power  
and Ground Planes to improve noise immunity  
• Any combination of sectors can be erased. Also  
supports full chip erase.  
Minimum 100,000 Write/Erase Cycles Minimum  
*This data sheet describes a product under development, not fully  
characterized, and is subject to change without notice.  
Note:  
For programming information refer to Flash Programming 16M5  
Application Note.  
FIG. 1 PIN CONFIGURATION FOR WF4M32-XH2X5  
PIN DESCRIPTION  
TOP VIEW  
I/O0-31 Data Inputs/Outputs  
1
12  
23  
34  
45  
56  
A0-21  
WE  
Address Inputs  
Write Enables  
Chip Selects  
Output Enable  
Power Supply  
Ground  
I/O  
8
9
RESET  
I/O15  
I/O14  
I/O13  
I/O12  
OE  
I/O24  
I/O25  
I/O26  
V
CC  
I/O31  
I/O30  
I/O29  
I/O28  
CS1-4  
OE  
I/O  
CS  
2
CS4  
I/O10  
GND  
I/O11  
NC  
VCC  
GND  
RESET  
A
A
A
A
A
14  
16  
11  
0
A
7
I/O27  
Reset  
A
A
A
V
10  
A
A
A
12  
21  
13  
A
A
A
4
5
6
A1  
A2  
A3  
9
A
17  
BLOCK DIAGRAM  
15  
CC  
WE  
CS  
CS  
3
CS  
4
1
CS  
2
A
21  
18  
I/O  
I/O  
I/O  
I/O  
7
A
8
A20  
CS  
I/O23  
I/O22  
I/O21  
I/O20  
I/O0  
I/O1  
I/O2  
CS  
1
6
5
4
I/O16  
I/O17  
I/O18  
3
OE  
WE  
A19  
GND  
I/O19  
A
0-20  
RESET  
2M x 8  
2M x 8  
2Mx 8  
2M x 8  
I/O3  
2M x 8  
2M x 8  
2M x 8  
2M x 8  
11  
22  
33  
44  
55  
66  
I/O16-23  
I/O24-31  
I/O0-7  
I/O8-15  
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
December2003 Rev.5  

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