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WF128K32-90H1C5A PDF预览

WF128K32-90H1C5A

更新时间: 2024-10-30 20:24:15
品牌 Logo 应用领域
玛居礼 - MERCURY 内存集成电路
页数 文件大小 规格书
15页 241K
描述
Flash Module, 128KX32, 90ns, CPGA66, 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66

WF128K32-90H1C5A 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PGA,Reach Compliance Code:compliant
风险等级:5.71Is Samacsys:N
最长访问时间:90 nsJESD-30 代码:S-CPGA-P66
长度:27.3 mm内存密度:4194304 bit
内存集成电路类型:FLASH MODULE内存宽度:32
功能数量:1端子数量:66
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX32
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
编程电压:5 V认证状态:Not Qualified
座面最大高度:4.34 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:27.3 mm
Base Number Matches:1

WF128K32-90H1C5A 数据手册

 浏览型号WF128K32-90H1C5A的Datasheet PDF文件第2页浏览型号WF128K32-90H1C5A的Datasheet PDF文件第3页浏览型号WF128K32-90H1C5A的Datasheet PDF文件第4页浏览型号WF128K32-90H1C5A的Datasheet PDF文件第5页浏览型号WF128K32-90H1C5A的Datasheet PDF文件第6页浏览型号WF128K32-90H1C5A的Datasheet PDF文件第7页 
WF128K32-XXX5  
128KX32 5V FLASH MODULE, SMD 5962-94716  
FEATURES  
Access Times of 50*, 60, 70, 90, 120, 150ns  
Commercial, Industrial and Military Temperature Ranges  
5 Volt Programming. 5V ± 10% Supply  
Packaging:  
• 66 pin, PGA Type, 1.075 inch square, Hermetic  
Ceramic HIP (Package 400)  
Low Power CMOS, 1mA Standby Typical  
Embedded Erase and Program Algorithms  
TTL Compatible Inputs and CMOS Outputs  
• 68 lead, 40mm, Low Profile 3.5mm (0.140"), CQFP  
(Package 502)  
• 68 lead, Hermetic CQFP, 22.4mm (0.880 inch) square.  
Designed to fit JEDEC 68 lead 0.990" CQFJ footprint.  
Built-in Decoupling Caps and Multiple Ground Pins for  
Low Noise Operation  
Page Program Operation and Internal Program Control Time  
– G2 (Package 500), 5.08mm (0.200 inch) high  
– G2U (Package 510), 3.56mm (0.140 inch) high  
Weight  
WF128K32-XG2X5 - 8 grams typical  
WF128K32-XG2UX5 - 8 grams typical  
WF128K32-XH1X5 - 13 grams typical  
WF128K32-XG4TX5 - 20 grams typical  
Sector Architecture  
• 8 equal size sectors of 16KBytes each  
• Any combination of sectors can be concurrently erased.  
Also supports full chip erase  
Note: See programming information 1M5 in programming section for  
algorithms.  
100,000 Erase/Program Cycles Typical, 0°C to +70°C  
Organized as 128Kx32  
*
The access time of 50ns is only available in Industrial and Commercial  
temperature ranges only.  
FIG. 1 PIN CONFIGURATION FOR WF128K32N-XH1X5  
TOP VIEW  
PIN DESCRIPTION  
1
12  
23  
34  
45  
56  
I/O0-31  
Data Inputs/Outputs  
I/O8  
I/O9  
I/O10  
A14  
A16  
A11  
A0  
WE2  
CS2  
GND  
I/O11  
A10  
I/O15  
I/O14  
I/O13  
I/O12  
OE  
I/O24  
I/O25  
I/O26  
A7  
VCC  
CS4  
WE4  
I/O27  
A4  
I/O31  
I/O30  
I/O29  
I/O28  
A1  
A0-16  
WE1-4  
CS1-4  
OE  
Address Inputs  
Write Enables  
Chip Selects  
Output Enable  
Power Supply  
Ground  
VCC  
A12  
GND  
NC  
A9  
NC  
NC  
A5  
A2  
Not Connected  
A15  
WE1  
I/O7  
I/O6  
I/O5  
I/O4  
A13  
A6  
A3  
BLOCK DIAGRAM  
WE1CS1  
WE2CS2  
WE3CS3  
WE4CS4  
NC  
VCC  
CS1  
NC  
A8  
WE3  
CS3  
GND  
I/O19  
I/O23  
I/O22  
I/O21  
I/O20  
OE  
0-16  
A
I/O0  
I/O1  
I/O2  
I/O16  
I/O17  
I/O18  
128K x 8  
128K x 8  
128K x 8  
128K x 8  
I/O3  
8
8
8
8
11  
22  
33  
44  
55  
66  
I/O16-23  
I/O24-31  
I/O0-7  
I/O8-15  
October 1998  
1
White Microelectronics • Phoenix, AZ • (602) 437-1520  

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