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WEDPN16M64V-133B2C

更新时间： 2024-09-26 03:30:19

品牌	Logo	应用领域
WEDC		内存集成电路动态存储器
页数	文件大小	规格书
15页	572K
描述
16Mx64 Synchronous DRAM

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WEDPN16M64V-XB2X

White Electronic Designs

16Mx64 Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

ꢀ

High Frequency = 100, 125, 133MHz

Package:

The 128MByte (1Gb) SDRAM is a high-speed CMOS,

dynamic random-access, memory using 4 chips containing

268,435,456 bits. Each chip is internally conﬁ g ured as a

quad-bank DRAM with a synchronous interface. Each of

the chip’s 67,108,864-bit banks is organized as 8,192 rows

by 512 columns by 16 bits.

• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm

Single 3.3V 0.3V power supply

Fully Synchronous; all signals registered on positive

edge of system clock cycle

ꢀ

Read and write accesses to the SDRAM are burst

oriented; accesses start at a selected location and

continue for a programmed number of locations in

a programmedsequence. Accesses begin with the

registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command are

used to select the bank and row to be accessed (BA0, BA1

select the bank; A0-12 select the row). The address bits

registered coincident with the READ or WRITE command

are used to select the starting column location for the

burst access.

ꢀ

Internal pipelined operation; column address can be

changed every clock cycle

Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

8,192 refresh cycles

Commercial, Industrial and Military Temperature

Ranges

Organized as 16M x 64

ꢀ

•

User conﬁgurable as 2 x 16M x 32 and 4 x 16M

x 16

ꢀ

Weight: WEDPN16M64V-XB2X - 2.0 grams typical

The SDRAM provides for programmable READ or WRITE

burst lengths of 1, 2, 4 or 8 locations, or the full page, with

a burst terminate option.AnAUTO PRECHARGE function

may be enabled to provide a self-timed row precharge that

is initiated at the end of the burst sequence.

BENEFITS

ꢀ

58% SPACE SAVINGS

Reduced part count

Reduced trace lengths for lower parasitic

capacitance

Suitable for hi-reliability applications

Laminate interposer for optimum TCE match

Upgradeable to 32M x 64 density

(W332M64V-XBX)

The 1Gb SDRAM uses an internal pipelined architecture

to achieve high-speed operation. This architecture is

compatible with the 2n rule of prefetch architectures, but

it also allows the column address to be changed on every

clock cycle to achieve a high-speed, fully random access.

Precharging one bank while accessing one of the other

three banks will hide the precharge cycles and provide

seamless, high-speed, random-access operation.

ꢀ

* This product is subject to change without notice.

Discrete Approach

ACTUAL SIZE

WEDPN16M64V-XB2X

Area

4 x 265mm²= 1060mm²

441mm²

58%

January 2005

Rev. 1

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...15

中文翻译

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与WEDPN16M64V-133B2C相关器件

型号	品牌	获取价格	描述	数据表
WEDPN16M64V-133B2I	WEDC	获取价格	16Mx64 Synchronous DRAM
WEDPN16M64V-133B2I	MERCURY	获取价格	Synchronous DRAM, 16MX64, 5.5ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN16M64V-133B2I	MICROSEMI	获取价格	Synchronous DRAM, 16MX64, 5.5ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN16M64V-133B2M	WEDC	获取价格	16Mx64 Synchronous DRAM
WEDPN16M64V-133B2M	MERCURY	获取价格	Synchronous DRAM, 16MX64, 5.5ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN16M64V-133B2M	MICROSEMI	获取价格	Synchronous DRAM, 16MX64, 5.5ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN16M64VR-100B2C	WEDC	获取价格	16Mx64 REGISTERED SYNCHRONOUS DRAM
WEDPN16M64VR-100B2C	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX64, 6ns, CMOS, PBGA219, 25 X 21 MM, PLASTIC, BGA-219
WEDPN16M64VR-100B2I	WEDC	获取价格	16Mx64 REGISTERED SYNCHRONOUS DRAM
WEDPN16M64VR-100B2I	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX64, 6ns, CMOS, PBGA219, 25 X 21 MM, PLASTIC, BGA-219

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