Datasheet > WEDPN16M64V-100B2M

WEDPN16M64V-100B2M

更新时间： 2024-02-13 11:38:14

品牌	Logo	应用领域
玛居礼 - MERCURY		动态存储器内存集成电路
页数	文件大小	规格书
13页	916K
描述
Synchronous DRAM, 16MX64, 7ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219

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WEDPN16M64V-100B2M 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	21 X 21 MM, PLASTIC, BGA-219	Reach Compliance Code：	unknown
风险等级：	5.68	Is Samacsys：	N
访问模式：	MULTI BANK PAGE BURST	最长访问时间：	7 ns
其他特性：	AUTO REFRESH	JESD-30 代码：	S-PBGA-B219
内存密度：	1073741824 bit	内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	64	功能数量：	1
端口数量：	1	端子数量：	219
字数：	16777216 words	字数代码：	16000000
工作模式：	SYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	16MX64
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

WEDPN16M64V-100B2M 数据手册

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WEDPN16M64V-XB2X

*PRELIMINARY

16Mx64 Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

 High Frequency = 100, 125, 133MHz

The 128MByte (1Gb) SDRAM is a high-speed CMOS, dynamic

random-access, memory using 4 chips containing 268,435,456

bits. Each chip is internally conﬁgured as a quad-bank DRAM with

a synchronous interface. Each of the chip’s 67,108,864-bit banks

is organized as 8,192 rows by 512 columns by 16 bits.

 Package:

• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm

 Single 3.3V ±0.3V power supply

 Fully Synchronous; all signals registered on positive edge

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a programmed

number of locations in a programmedsequence. Accesses begin

with the registration of anACTIVE command, which is then followed

by a READ or WRITE command. The address bits registered

coincident with the ACTIVE command are used to select the bank

and row to be accessed (BA0, BA1 select the bank; A0-12 select

the row). The address bits registered coincident with the READ or

WRITE command are used to select the starting column location

for the burst access.

of system clock cycle

 Internal pipelined operation; column address can be

changed every clock cycle

 Internal banks for hiding row access/precharge

 Programmable Burst length 1,2,4,8 or full page

 8,192 refresh cycles

 Commercial, Industrial and Military Temperature Ranges

 Organized as 16M x 64

The SDRAM provides for programmable READ or WRITE burst

lengths of 1, 2, 4 or 8 locations, or the full page, with a burst

terminate option.AnAUTO PRECHARGE function may be enabled

to provide a self-timed row precharge that is initiated at the end

of the burst sequence.

• User conﬁgurable as 2 x 16M x 32 and 4 x 16M x 16

 Weight: WEDPN16M64V-XB2X - 2.0 grams typical

BENEFITS

The 1Gb SDRAM uses an internal pipelined architecture to achieve

high-speed operation. This architecture is compatible with the 2n

rule of prefetch architectures, but it also allows the column address

to be changed on every clock cycle to achieve a high-speed, fully

random access. Precharging one bank while accessing one of

the other three banks will hide the precharge cycles and provide

seamless, high-speed, random-access operation.

 58% SPACE SAVINGS

 Reduced part count

 Reduced trace lengths for lower parasitic capacitance

 Suitable for hi-reliability applications

 Laminate interposer for optimum TCE match

 Upgradeable to 32M x 64 density

The 1Gb SDRAM is designed to operate in 3.3V, low-power

memory systems. An auto refresh mode is provided, along with a

power-saving, power-down mode.

(W332M64V-XBX)

* This product is subject to change without notice.

All inputs and outputs are LVTTL compatible. SDRAMs offer

substantial advances in DRAM operating performance, including

the ability to synchronously burst data at a high data rate with

automatic column-address generation, the ability to interleave

between internal banks in order to hide precharge time and the

continued on page 4

DENSITY COMPARISONS

Discrete Approach (mm)

WEDPN16M64V-XB2X

11.9

TSOP

22.3

WEDPN16M64V-XB2X

Area

4 x 265mm²= 1,060mm²

441mm²

58%

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 1

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

12 3 4 5 6 7...13

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与WEDPN16M64V-100B2M相关器件

型号	品牌	获取价格	描述	数据表
WEDPN16M64V-125B2C	WEDC	获取价格	16Mx64 Synchronous DRAM
WEDPN16M64V-125B2C	MERCURY	获取价格	Synchronous DRAM, 16MX64, 6ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN16M64V-125B2C	MICROSEMI	获取价格	Synchronous DRAM, 16MX64, 6ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN16M64V-125B2I	WEDC	获取价格	16Mx64 Synchronous DRAM
WEDPN16M64V-125B2I	MICROSEMI	获取价格	Synchronous DRAM, 16MX64, 6ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN16M64V-125B2M	MICROSEMI	获取价格	Synchronous DRAM, 16MX64, 6ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN16M64V-125B2M	WEDC	获取价格	16Mx64 Synchronous DRAM
WEDPN16M64V-125B2M	MERCURY	获取价格	Synchronous DRAM, 16MX64, 6ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219
WEDPN16M64V-133B2C	WEDC	获取价格	16Mx64 Synchronous DRAM
WEDPN16M64V-133B2C	MERCURY	获取价格	Synchronous DRAM, 16MX64, 5.5ns, CMOS, PBGA219, 21 X 21 MM, PLASTIC, BGA-219

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