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WED9LAPC2C16P8BI PDF预览

WED9LAPC2C16P8BI

更新时间: 2024-11-21 03:28:39
品牌 Logo 应用领域
WEDC 内存集成电路动态存储器
页数 文件大小 规格书
21页 693K
描述
4M x 32 SDRAM / 2M x 8 SDRAM

WED9LAPC2C16P8BI 数据手册

 浏览型号WED9LAPC2C16P8BI的Datasheet PDF文件第2页浏览型号WED9LAPC2C16P8BI的Datasheet PDF文件第3页浏览型号WED9LAPC2C16P8BI的Datasheet PDF文件第4页浏览型号WED9LAPC2C16P8BI的Datasheet PDF文件第5页浏览型号WED9LAPC2C16P8BI的Datasheet PDF文件第6页浏览型号WED9LAPC2C16P8BI的Datasheet PDF文件第7页 
WED9LAPC2B16P8BC  
White Electronic Designs  
4M x 32 SDRAM / 2M x 8 SDRAM  
EXTERNAL MEMORY SOLUTION FOR AGERE’S TAPC640 ATM PORT CONTROLLER  
FEATURES  
DESCRIPTION  
Clock speeds:  
TheWED9LAPC2B16P8BCisa3.3V, 4Mx32Synchronous  
DRAM and a 2M x 8 Synchronous DRAM array packaged  
in a 14mm x 22mm 153 lead BGA.  
• SDRAM: 100 MHz  
100% tested to timing requirements of TAPC640’s  
memory interface  
The WED9LAPC2B16P8BC provides the memory required  
for the BRAM (Buffer Memory) and PRAM (Pointer Memory)  
memory ports for Agere’s TAPC640 ATM port controller.  
When used in conjunction with the WED9LAPC2C16V4BC,  
which provides memory for the CRAM (Control Memory)  
and VCRAM (Virtual Control Memory) memory ports, the  
entire memory requirement of the LUCTAPC640 can be  
met using these 2 BGA devices.  
Packaging:  
• 153 pin BGA, 14mm x 22mm  
3.3V Operating supply voltage  
Direct control interface to both the BRAM and  
PRAM ports on the TAPC640  
62% space savings vs. monolithic solution  
Reduced system inductance and capacitance  
The WED9LAPC2B16P8BC is 100% tested to the timing  
requirements of the TAPC640’s memory interface timing  
for both Commercial and Industrial temperature ranges.  
FIGURE 1 – PIN CONFIGURATION  
Pinout BRAM and PRAM MCM — Top View  
1
A
B
C
D
E
F
G
H
J
2
VCC  
3
4
5
VSS  
6
7
VSS  
8
9
BDATA_A  
BDATA_A  
GCLK  
BWEN  
BCASN  
BRASN  
BDQM  
BDATA_A  
BDATA_A  
VSS  
BDATA_A  
BDATA_A  
BDATA_A  
BDATA_A  
BDATA_A  
BDATA_B  
BDATA_B  
BDATA_B  
BDATA_B  
BDATA_B  
BDATA_B  
VCC  
BDATA_A  
BDATA_A  
BDATA_A  
BDATA_A  
BDATA_A  
BDATA_B  
BDATA_B  
BDATA_B  
BDATA_B  
BDATA_B  
BDATA_B  
VSS  
VSS  
VCC  
VCC  
VCC  
VSS  
VSS  
VSS  
VCC  
VCC  
VCC  
VSS  
VSS  
VSS  
VSS  
VCC  
VCC  
VSS  
NC  
NC  
NC  
VCC  
VSS  
VCC  
BADDR9  
BADDR7  
BADDR5  
BADDR3  
VCC  
BADDR11  
BADDR8  
BADDR6  
BADDR4  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
NC  
VSS  
VSS  
VSS  
VSS  
NC  
VSS  
BDATA_A  
BDATA_A  
VCC  
VSS  
VSS  
VCC  
VSS  
BDATA_B  
BDATA_B  
VSS  
BADDR1  
BADDR10  
BADDR2  
BADDR0  
NC  
VSS  
NC  
NC  
VSS  
BADDR12 BADDR13  
K
L
BDATA_B  
BDATA_B  
VCC  
NC  
NC  
VCC  
VSS  
VCC  
VCC  
NC  
NC  
PADDR8  
PADDR6  
PADDR4  
PADDR2  
PADDR0  
PBS  
PADDR9  
PADD7  
M
N
P
R
T
NC  
NC  
VSS  
PDATA  
PDATA  
VSS  
NC  
NC  
VSS  
PADDR5  
PADDR3  
PADDR1  
PADDR10  
PDATA  
VCC  
VSS  
NC  
NC  
VSS  
PDATA  
VCC  
PDATA  
VCC  
PCASN  
VCC  
PRASN  
PDQM  
PWEN  
PDATA  
PDATA  
PDATA  
U
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
November 2001  
Rev. 1  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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