A1008U1X
WCMA1008U1X
128K x 8 Static RAM
ic power-down feature, reducing the power consumption by
over 99% when deselected.
Features
• High Speed
Writing to the device is accomplished by taking Chip Enable
one (CE1) and Write Enable (WE) inputs LOW and the Chip
Enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
— 55ns and 70ns availability
• Voltage range
— 2.7V–3.6V
• Ultra low active power
— Typical active current: 20 mA @ f = fmax (70ns speed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Reading from the device is accomplished by taking Chip En-
able one (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
Functional Description
The WCMA1008U1X is a high-performance CMOS static
RAM organized as 128K words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE1), an ac-
tive HIGH Chip Enable (CE2), an active LOW Output Enable
(OE) and three-state drivers. These devices have an automat-
The WCMA1008U1X is available in a 32 Lead TSOP and
STSOP packages.
Logic Block Diagram
Pin Configurations
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
24
23
OE
A10
25
26
2268
7
22
21
20
19
18
17
16
15
14
13
12
11
10
9
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
29
30
31
32
1
2
3
4
5
6
7
8
STSOP
Top View
(not to scale)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A1
A2
A3
0
INPUT BUFFER
1
2
A
0
A
A
A
A
8
1
2
32
OE
1
11
31
30
29
28
27
26
25
24
23
22
21
20
A
9
A
10
2
3
4
5
6
7
8
CE
1
A
3
A
I/O
I/O
I/O
13
7
6
5
A
WE
CE
4
512x256x8
ARRAY
3
4
5
2
A
5
A
TSOP I
Top View
(not to scale)
15
I/O
I/O
4
A
6
V
CC
3
NC
9
GND
A
7
A
I/O
10
11
12
13
14
15
16
16
2
A
8
I/O
1
A
14
A
I/O
12
0
A
A
6
A
A
4
A
0
7
A
19
18
17
1
A
2
5
POWER
DOWN
6
7
A
3
COLUMN
DECODER
CE
1
2
CE
I/O
WE
OE