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WCMA1008C1X-GF70 PDF预览

WCMA1008C1X-GF70

更新时间: 2024-01-20 11:15:31
品牌 Logo 应用领域
韦达 - WEIDA /
页数 文件大小 规格书
11页 208K
描述
128K x 8 Static RAM

WCMA1008C1X-GF70 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:NBase Number Matches:1

WCMA1008C1X-GF70 数据手册

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WCMA1008C1X  
128K x 8 Static RAM  
(OE), and three-state drivers. This device has an automatic  
power-down feature that reduces power consumption by more  
than 75% when deselected.  
Features  
• Voltage Range  
4.5V–5.5V  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2  
(CE2) input HIGH. Data on the eight I/O pins (I/O0 through  
I/O7) is then written into the location specified on the address  
pins (A0 through A16).  
• Low active power  
— Typical active current: 6 mA @ f = fmax (70 ns speed)  
• Low standby current  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1, CE2, and OE fea-  
tures  
Reading from the device is accomplished by taking Chip En-  
able 1 (CE1) and Output Enable (OE) LOW while forcing Write  
Enable (WE) and Chip Enable 2 (CE2) HIGH. Under these  
conditions, the contents of the memory location specified by  
the address pins will appear on the I/O pins.  
• CMOS for optimum speed/power  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW)  
Functional Description  
The WCMA1008C1X is a high-performance CMOS static  
RAM organized as 128K words by 8 bits. Easy memory expan-  
sion is provided by an active LOW Chip Enable (CE1), an ac-  
tive HIGH Chip Enable (CE2), an active LOW Output Enable  
The WCMA1008C1X is available in a standard 32-pin  
450-mil-wide body width SOIC and 32-pin TSOP type I.  
Logic Block Diagram  
Pin  
Configuration  
Top View  
SOIC  
VCC  
A15  
A18  
A17  
A16  
32  
31  
30  
1
2
3
4
5
6
7
I/O  
0
1
2
INPUT BUFFER  
A14  
A12  
A7  
A6  
I/O  
I/O  
29  
28  
27  
26  
WE  
A13  
A8  
A
A
A
0
1
2
A
A
A
A
A
A
A5  
3
4
5
6
7
8
A9  
I/O  
I/O  
I/O  
25  
24  
23  
22  
21  
A4  
A3  
A2  
3
4
5
512x256x8  
ARRAY  
8
9
10  
11  
12  
13  
A11  
OE  
A10  
CE  
I/O7  
I/O6  
I/O5  
A1  
A0  
I/O0  
20  
19  
I/O  
I/O  
6
7
I/O1  
I/O2  
GND  
POWER  
DOWN  
14  
15  
16  
COLUMN  
DECODER  
CE  
CE  
1
I/O4  
I/O3  
18  
17  
2
WE  
OE  
A
1
32  
31  
OE  
10  
11  
9
2
A
A
3
A
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
CE  
8
13  
1
4
A
I/O  
7
6
5
4
3
5
WE  
I/  
/
O6  
O
6
CE  
2
I/O  
I/O  
I/O  
A
7
TSOP I  
Top View  
(not to scale)  
15  
CC  
8
V
NC  
9
GND  
A
I/O  
2
10  
11  
12  
13  
14  
15  
16  
16  
I/O  
1
A
14  
12  
A
I/O  
0
A
7
A
0
A
1
A
6
A
5
A
2
A
3
A
4
April 5, 2002  

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