Datasheet > W88112D

W88112D

更新时间： 2024-11-05 19:46:07

品牌	Logo	应用领域
华邦 - WINBOND		/
页数	文件大小	规格书
64页	449K
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数据手册

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W88112D 数据手册

W88111AF/W88112F

ATAPI CD-ROM Decoder & Controller

This specification is subject to change without notice.

Preliminary/Confidential

Table Of Contents

GENERAL DESCRIPTION ________________________________________________________________5

BLOCK DIAGRAM_______________________________________________________________________6

PIN CONFIGURATION ___________________________________________________________________7

PIN DESCRIPTIONS______________________________________________________________________8

REGISTERS DESCRIPTION______________________________________________________________12

IR - Index Register (read/write) ____________________________________________________________12

PFAR - Packet FIFO Access Register - (read 00h) _____________________________________________12

INTCTL - Interrupt Control Register - (write 01h) _____________________________________________12

INTREA - Interrupt Reason Register - (read 01h)______________________________________________13

TBCL/TBCH - Transfer Byte/Word Counter - (read/write 02h/03h)________________________________15

TACL/TACH - Transfer Address Counter - (write 04h/05h) ______________________________________15

TBL/TBH - Transfer Block Register - (read/write 24h/25h) ______________________________________15

THTRG - Transfer to Host Trigger Register - (write 06h)________________________________________15

TACK - Transfer Acknowledge - (write 07h) __________________________________________________16

HEAD0 to HEAD3 - Header Registers - (read 03h to 07h)_______________________________________16

BIAL/BIAH - Buffering Initial Address Register - (write 08h/09h) _________________________________16

BACL, BACH - Buffering Address Counter - (read 0Ah/0Bh)_____________________________________16

EIAL/EIAH - ECC Initial Address Register- (read 08h/09h, write 0Ch/0Dh)_________________________16

SCBL/SCBH - Subcode Block Register - (read/write 26h/27h) ____________________________________17

DDBL/DDBH - Decoded Data Block Register - (read/write 28h/29h) ______________________________17

CTRL0 - Control Register 0 - (write 0Ah) ____________________________________________________17

CTRL1 - Control Register 1 - (write 0Bh) ____________________________________________________18

STAT0 - Status Register 0 - (read 0Ch) ______________________________________________________19

STAT1 - Status Register 1 - (read 0Dh) ______________________________________________________20

DHTACK - DRAM to Host Transfer Acknowledge - (write 0Eh) __________________________________21

STAT2 - Status Register 2 - (read 0Eh) ______________________________________________________21

FRST - Firmware Reset Register - (write 0Fh) ________________________________________________22

Publication Release Date: Aug, 1996

- 1 -

Preliminary/Confidential Revision A0.1

12 3 4 5 6 7...64

中文翻译

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与W88112D相关器件

型号	品牌	获取价格	描述	数据表
W88112F	WINBOND	获取价格	ATAPI CD-ROM DECODER & CONTROLLER
W88113C	WINBOND	获取价格	ATAPI CD-ROM DECODER & CONTROLLER
W88113CD	WINBOND	获取价格	ATAPI CD-ROM DECODER & CONTROLLER
W88113CF	WINBOND	获取价格	ATAPI CD-ROM DECODER & CONTROLLER
W88227F	WINBOND	获取价格	Consumer Circuit, PQFP128, PLASTIC, QFP-128
W88227QD	WINBOND	获取价格	Consumer Circuit, PQFP128, LQFP-128
W88611P	WINBOND	获取价格	VCD 4X RF AMP/DIGITAL SERVO & DSP
W88631F	WINBOND	获取价格	VCD 4X RF AMP/DIGITAL SERVO & DSP
W8880-10PG-300W	ETC	获取价格	Available with 9 or 10 #22 contacts
W8880-10PG-3ESW	ETC	获取价格	Available with 9 or 10 #22 contacts

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