W78M32VP-XBX
8Mx32 NOR Flash 3.3V Page Mode Multi-Chip Package
FEATURES
GENERAL DESCRIPTION
Access Times of 110, 120ns
The W78M32VP-XBX is a 256Mb, 3.3 volt-only Page Mode
memory device.
Packaging
The device offers fast page access times allowing high speed
microprocessors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CS#), write enable
(WE#) and output enable (OE#) controls.
• 159 PBGA, 13x22mm – 1.27mm pitch
Page Mode
• Page size is 8 words: Fast page read access from
random locations within the page.
The device offers uniform 64 Kword (128Kb) Sectors:
Uniform Sector Architecture
• One hundred twenty-eight 64 kword
Single power supply operation
• 3 volt read, erase, and program operations
I/O Control
PAGE MODE FEATURES
The page size is 8 words.After initial page access is accomplished,
the page mode operation provides fast read access speed of
random locations within that page.
STANDARD FLASH MEMORY FEATURES
The device requires a 3.3 volt power supply for both read and write
functions. Internally generated and regulated voltages are provided
for the program and erase operations Page Mode Features
• All input levels (address, control, and DQ input levels)
and outputs are determined by voltage on VIO input. VIO
range is 1.65 to VCC
Write operation status bits indicate program and erase
operation completion
DEVICE OPERATIONS
Suspend and Resume commands for program and erase
This section describes the read, program, erase, handshaking,
and reset features of the Flash devices. Operations are initiated by
writing specific commands or a sequence with specific address and
data patterns into the command registers ( see Table 38 and Table
39). The command register itself does not occupy andy addressable
memory location; rather, it is composed of latches that store the
commands, along with the address and data information needed
to execute the command. The contents of the register serves as
input to the internal state machine and the state machine outputs
dictate the function of the device. Writing incorrect address and
data values or writing them in an improper sequence may place
the device in an unknown state, in which case the system must
pull the RESET# pin low or power cycle the device to return the
device to the reading array data mode.
operations
Hardware Reset# input resets device
WP#/ACC Input
• Accelerates programming time for greater throughput.
• Protects first and last sector regardless of sector
protection settings
Secured Silicon Sector region
• 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number,
accessible through a command sequence
• May be programmed and locked at the factory or by the
customer
100,000 erase cycles per sector typical
20-year data retention typical
DEVICE OPERATION TABLE
The device must be setup appropriately for each operation. Table
2 describes the required state of each control pin for any particular
operation.
* This product is subject to change without notice.
VersatileIO™ (VIO) CONTROL
The VersatileIO™ (VIO) control allows the host system to set the
voltage levels that the device generates and tolerates on all inputs
and outputs (address, control, and DQ signals). VIO range is 1.65
to VCC
.
For example, a VIO of 1.65-3.6 volts allows for I/O at the 1.8 or 3
volt levels, driving and receiving signals to and from other 1.8 or
3 V devices on the same data bus.
Continued on page 3
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2011 © 2011 Microsemi Corporation. All rights reserved.
Rev. 15
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