W66BL6NB / W66CL2NQ
2Gb / 4Gb LPDDR4
Table of Contents-
1.
2.
3.
4.
GENERAL DESCRIPTION ............................................................................................................................................ 5
FEATURES.................................................................................................................................................................... 5
ORDER INFORMATION................................................................................................................................................ 5
BALL ASSIGNMENT ..................................................................................................................................................... 6
Single-Die-Package (SDP) WFBGA 200 Ball Assignment............................................................................................. 6
Dual-Die-Package (DDP) WFBGA 200 Ball Assignment ............................................................................................... 7
BALL CONFIGURATION ............................................................................................................................................... 8
Ball Description.............................................................................................................................................................. 8
Addressing Table........................................................................................................................................................... 9
BLOCK DIAGRAM....................................................................................................................................................... 10
Block diagram of single chip ........................................................................................................................................ 10
Block diagram of Dual-Die-Package (DDP) ................................................................................................................. 11
FUNCTIONAL DESCRIPTION..................................................................................................................................... 12
Simplified LPDDR4 State Diagram .............................................................................................................................. 12
4.1
4.2
5.
6.
7.
5.1
5.2
6.1
6.2
7.1
7.2
7.1.1
Simplified Bus Interface State Diagram ....................................................................................................................... 13
Power-up, Initialization, and Power-Off Procedure ...................................................................................................... 15
7.2.1
Voltage Ramp and Device Initialization........................................................................................................................ 15
Reset Initialization with Stable Power .......................................................................................................................... 17
Power-off Sequence.................................................................................................................................................... 17
Uncontrolled Power-Off Sequence .............................................................................................................................. 18
7.2.2
7.2.3
7.2.4
7.3
Mode Register Definition.............................................................................................................................................. 19
7.3.1
MR0 Register Information (MA[5:0] = 00 ).................................................................................................................. 20
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7.3.2
MR1 Register Information (MA[5:0] = 01 ).................................................................................................................. 21
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7.3.3
MR2 Register Information (MA[5:0] = 02 ).................................................................................................................. 23
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7.3.4
MR3 Register Information (MA[5:0] = 03 ).................................................................................................................. 24
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7.3.5
MR4 Register Information (MA[5:0] = 04 ).................................................................................................................. 25
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7.3.6
MR5 Register Information (MA[5:0] = 05 ).................................................................................................................. 26
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7.3.7
MR6 Register Information (MA[5:0] = 06 ).................................................................................................................. 26
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7.3.8
MR7 Register Information (MA[5:0] = 07 ).................................................................................................................. 26
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7.3.9
MR8 Register Information (MA[5:0] = 08 ).................................................................................................................. 26
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7.3.10
7.3.11
7.3.12
7.3.13
7.3.14
7.3.15
7.3.16
7.3.17
7.3.18
7.3.19
7.3.20
7.3.21
7.3.22
7.3.23
7.3.24
7.3.25
7.3.26
7.3.27
MR9 Register Information (MA[5:0] = 09 ).................................................................................................................. 26
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MR10 Register Information (MA[5:0] = 0A ) ............................................................................................................... 26
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MR11 Register Information (MA[5:0] = 0B ) ............................................................................................................... 27
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MR12 Register Information (MA[5:0] = 0C ) ............................................................................................................... 27
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MR13 Register Information (MA[5:0] = 0D ) ............................................................................................................... 29
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MR14 Register Information (MA[5:0] = 0E ) ............................................................................................................... 30
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MR15 Register Information (MA[5:0] = 0F )................................................................................................................ 32
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MR16 Register Information (MA[5:0] = 10 )................................................................................................................ 33
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MR17 Register Information (MA[5:0] = 11 )................................................................................................................ 33
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MR18 Register Information (MA[5:0] = 12 )................................................................................................................ 34
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MR19 Register Information (MA[5:0] = 13 )................................................................................................................ 34
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MR20 Register Information (MA[5:0] = 14 )............................................................................................................... 34
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MR21 Register (Reserved) (MA[5:0] = 15 )................................................................................................................ 34
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MR22 Register Information (MA[5:0] = 16 )................................................................................................................ 35
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MR23 Register Information (MA[5:0] = 17 )................................................................................................................ 36
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MR24 Register Information (MA[5:0] = 18 )................................................................................................................ 36
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MR25 Register Information (MA[5:0] = 19 )................................................................................................................ 37
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MR26~29 (Reserved) (MA[5:0] = 1A -1D )................................................................................................................ 37
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Publication Release Date: Jul. 04, 2019
Revision: A01-001
- 1 -
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