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W632GG8KB-12 TR PDF预览

W632GG8KB-12 TR

更新时间: 2024-11-24 22:58:47
品牌 Logo 应用领域
其他 - ETC 动态存储器
页数 文件大小 规格书
159页 5237K
描述
IC DRAM 2G PARALLEL 78WBGA

W632GG8KB-12 TR 数据手册

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W632GG8KB  
32M 8 BANKS 8 BIT DDR3 SDRAM  
Table of Contents-  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
GENERAL DESCRIPTION ...................................................................................................................5  
FEATURES...........................................................................................................................................5  
ORDER INFORMATION.......................................................................................................................6  
KEY PARAMETERS .............................................................................................................................7  
BALL CONFIGURATION ......................................................................................................................8  
BALL DESCRIPTION............................................................................................................................9  
BLOCK DIAGRAM ..............................................................................................................................11  
FUNCTIONAL DESCRIPTION............................................................................................................12  
Basic Functionality ..............................................................................................................................12  
RESET and Initialization Procedure....................................................................................................12  
8.1  
8.2  
8.2.1  
8.2.2  
Power-up Initialization Sequence.....................................................................................12  
Reset Initialization with Stable Power ..............................................................................14  
8.3  
Programming the Mode Registers.......................................................................................................15  
8.3.1  
Mode Register MR0 .........................................................................................................17  
Burst Length, Type and Order ................................................................................17  
CAS Latency...........................................................................................................18  
Test Mode...............................................................................................................18  
DLL Reset...............................................................................................................18  
Write Recovery.......................................................................................................19  
Precharge PD DLL .................................................................................................19  
Mode Register MR1 .........................................................................................................19  
DLL Enable/Disable................................................................................................20  
Output Driver Impedance Control...........................................................................20  
ODT RTT Values....................................................................................................20  
Additive Latency (AL) .............................................................................................20  
Write leveling..........................................................................................................20  
Output Disable........................................................................................................21  
TDQS, TDQS#........................................................................................................21  
Mode Register MR2 .........................................................................................................22  
Partial Array Self Refresh (PASR)..........................................................................23  
CAS Write Latency (CWL)......................................................................................23  
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) .............................23  
Dynamic ODT (Rtt_WR).........................................................................................23  
Mode Register MR3 .........................................................................................................24  
Multi Purpose Register (MPR)................................................................................24  
8.3.1.1  
8.3.1.2  
8.3.1.3  
8.3.1.4  
8.3.1.5  
8.3.1.6  
8.3.2  
8.3.2.1  
8.3.2.2  
8.3.2.3  
8.3.2.4  
8.3.2.5  
8.3.2.6  
8.3.2.7  
8.3.3  
8.3.3.1  
8.3.3.2  
8.3.3.3  
8.3.3.4  
8.3.4  
8.3.4.1  
8.4  
8.5  
8.6  
8.7  
No OPeration (NOP) Command..........................................................................................................25  
Deselect Command.............................................................................................................................25  
DLL-off Mode ......................................................................................................................................25  
DLL on/off switching procedure...........................................................................................................26  
8.7.1  
8.7.2  
DLL onto DLL offProcedure..........................................................................26  
DLL offto DLL onProcedure..........................................................................27  
8.8  
Input clock frequency change .............................................................................................................28  
8.8.1  
8.8.2  
Frequency change during Self-Refresh............................................................................28  
Frequency change during Precharge Power-down..........................................................28  
Publication Release Date: Feb. 13, 2017  
Revision: A05  
- 1 -  

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