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W532

更新时间： 2024-11-09 03:17:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
8页	119K
描述
Frequency Multiplying, Peak Reducing EMI Solution

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W532 数据手册

W532

Frequency Multiplying, Peak Reducing EMI Solution

Table 1. Output Frequency Range Selection

Features

Output Range

• Cypress PREMIS™ family offering

• Generates an EMI optimized clocking signal at the

output

• Selectable frequency range and multiplication factor

• Single 1.25% or 5% center spread output

• Integrated loop filter components

• Operates with a 3.3V or 5V supply

• Low power CMOS design

OR2

OR1

(Multiplication Factor Selection)

reserved

15 MHz ≤ F_IN≤ 30 MHz

30 MHz ≤ F_IN≤ 60 MHz

60 MHz ≤ F_IN≤ 120 MHz

Table 2. Modulation Width Selection

• Available in 16-pin SOIC

Output

Key Specifications

_avg+ 0.625% ≥ F_out≥ F_avg– 0.625%

Supply Voltages:........................................V_DD= 3.3V ±0.3V

F_avg+ 2.5% ≥ F_out≥ F_avg– 2.5%

or V_DD= 5V ±10%

Frequency Range: .........................15 MHz ≤ F_out≤ 120 MHz

Cycle to Cycle Jitter: ......................................... 150 ps (typ.)

Output Duty Cycle: ............................... 40/60% (worst case)

Output Rise and Fall Time ................................... 5 ns (max.)

Table 3. Input Frequency Range Selection

IR2

IR1

Input Range

reserved

15 MHz ≤ F_IN≤ 30 MHz

30 MHz ≤ F_IN≤ 60 MHz

60 MHz ≤ F_IN≤ 120 MHz

Simplified Block Diagram

Pin Configuration

3.3V or 5.0V

SOIC

VDD

GND

XTAL

Input

AVDD

*OR1

IR1^

IR2^

Spread Spectrum

Output

(EMI suppressed)

W532

SSOUT

GND

AGND

^OR2

*SSON#

VDD

3.3V or 5.0V

MW*

Notes:

1. ^ pins have internal pull-up

2. * pins have internal pull-down

Oscillator or

Reference Input

Spread Spectrum

W532

Output

(EMI suppressed)

PREMIS is a trademark of Cypress Semiconductor.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07253 Rev. *A

Revised December 28, 2002

12 3 4 5 6 7 8

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