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W364M72V-133SBC

更新时间： 2024-11-05 20:04:31
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟动态存储器内存集成电路
页数 文件大小 规格书
14页 1117K
描述
Synchronous DRAM, 64MX72, 5.5ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219

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W364M72V-133SBC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA, BGA219,16X16,50针数：219
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.36风险等级：5.4
访问模式：FOUR BANK PAGE BURST最长访问时间：5.5 ns
其他特性：AUTO/SELF REFRESH最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B219
内存密度：4831838208 bit内存集成电路类型：SYNCHRONOUS DRAM
内存宽度：72功能数量：1
端口数量：1端子数量：219
字数：67108864 words字数代码：64000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64MX72
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA219,16X16,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified刷新周期：8192
自我刷新：YES最大待机电流：0.405 A
子类别：DRAMs最大压摆率：1.035 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

W364M72V-133SBC 数据手册

 浏览型号W364M72V-133SBC的Datasheet PDF文件第2页浏览型号W364M72V-133SBC的Datasheet PDF文件第3页浏览型号W364M72V-133SBC的Datasheet PDF文件第4页浏览型号W364M72V-133SBC的Datasheet PDF文件第5页浏览型号W364M72V-133SBC的Datasheet PDF文件第6页浏览型号W364M72V-133SBC的Datasheet PDF文件第7页 
W364M72V-XSBX  
64Mx72 Synchronous DRAM  
FEATURES  
BENEFITS  
 High Frequency = 100, 125, 133MHz  
 66% SPACE SAVINGS  
 Package:  
 Reduced part count from 9 to 1  
 Reduced I/O count  
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm  
 3.3V ±0.3V power supply for core and I/Os  
• 55% I/O Reduction  
 Fully Synchronous; all signals registered on positive edge  
 Reduced trace lengths for lower parasitic capacitance  
 Suitable for hi-reliability applications  
 Laminate interposer for optimum TCE match  
of system clock cycle  
 Internal pipelined operation; column address can be  
changed every clock cycle  
 Internal banks for hiding row access/precharge  
 Programmable Burst length 1,2,4,8 or full page  
 8,192 refresh cycles  
GENERAL DESCRIPTION  
The 512MByte (4.5Gb) SDRAM is a high-speed CMOS, dynamic  
random-access, memory using 9 chips containing 512M bits.  
Each chip is internally configured as a quad-bank DRAM with a  
synchronous interface. Each of the chip’s 134,217,728-bit banks  
is organized as 8,192 rows by 2,048 columns by 8 bits.  
 Commercial, Industrial and Military Temperature Ranges  
 Organized as 64M x 72  
 Weight: W364M72V-XSBX - TBD grams typical  
Read and write accesses to the SDRAM are burst oriented;  
accesses start at a selected location and continue for a  
programmed number of locations in a programmed sequence.  
Accesses begin with the registration of an ACTIVE command,  
which is then followed by a READ or WRITE command. The  
address bits registered coincident with the ACTIVE command  
are used to select the bank and row to be accessed (BA0, BA1  
select the bank; A0-12 select the row). The address bits registered  
coincident with the READ or WRITE command are used to select  
This product is subject to change without notice.  
the starting column location for the burst access.  
Continued on page 4  
DENSITY COMPARISONS  
W364M72V-XSBX  
25  
W364M72V-XSBX  
32  
Area = 800mm2  
I/O Count = 219 Balls  
SAVINGS — Area: 66%  
I/O Count: 55%  
Discrete Approach (mm)  
11.9  
11.9  
11.9  
11.9  
11.9  
11.9  
11.9  
11.9  
11.9  
54  
TSOP  
54  
TSOP  
54  
TSOP  
54  
TSOP  
54  
TSOP  
54  
TSOP  
54  
TSOP  
54  
TSOP  
54  
TSOP  
22.3  
Area 9 x 265mm2 = 2,385mm2  
I/O Count 9 x 54 pins = 486 pins  
Microsemi Corporation reserves the right to change products or specifications without notice.  
February 2011 © 2011 Microsemi Corporation. All rights reserved.  
Rev. 4  
1
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com  
www.microsemi.com  
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W364M72V-XSBX WEDC

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