Datasheet > 存储 > DRAM> W364M72V-125SBM

W364M72V-125SBM

更新时间： 2024-11-05 03:17:51

品牌	Logo	应用领域
WEDC		动态存储器
页数	文件大小	规格书
16页	495K
描述
64Mx72 Synchronous DRAM

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数据手册

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W364M72V-125SBM 数据手册

W364M72V-XSBX

White Electronic Designs

ADVANCED*

64Mx72 Synchronous DRAM

FEATURES

BENEFITS

ꢀ

High Frequency = 100, 125MHz

Package:

ꢀ

66% SPACE SAVINGS

Reduced part count from 9 to 1

• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm

3.3V 0.3V power supply for core and I/Os

Fully Synchronous; all signals registered on positive ꢀ Reduced trace lengths for lower parasitic

edge of system clock cycle capacitance

Reduced I/O count

• 55% I/O Reduction

ꢀ

Internal pipelined operation; column address can be ꢀ Suitable for hi-reliability applications

changed every clock cycle

ꢀ

Laminate interposer for optimum TCE match

ꢀ

Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

8,192 refresh cycles

Commercial, Industrial and Military Temperature

Ranges

Organized as 64M x 72

Weight: W364M72V-XSBX - TBD grams typical

GENERAL DESCRIPTION

The 512MByte (4.5Gb) SDRAM is a high-speed CMOS,

dynamic random-access, memory using 9 chips containing

512M bits. Each chip is internally conﬁgured as a quad-

bank DRAM with a synchronous interface. Each of the

chip’s 134,217,728-bit banks is organized as 8,192 rows

by 2,048 columns by 8 bits.

ꢀ

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a

* This product is under development, is not qualiﬁed or characterized and is subject to

change or cancellation without notice.

ACTUAL SIZE

White Electronic Designs

W364M72V-XSBX

Area = 800mm²

I/O Count = 219 Balls

SAVINGS – Area: 66% – I/O Count: 55%

Discrete Approach

11.9

TSOP

22.3

Area: 9 x 265mm²= 2,385mm²

I/O Count: 9 x 54 pins = 486 pins

January 2005

Rev. 1

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...16

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