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W305BH

更新时间： 2024-09-18 03:17:51
品牌 Logo 应用领域
SPECTRALINEAR 晶体外围集成电路光电二极管控制器时钟
页数 文件大小 规格书
20页 183K
描述
Frequency Controller with System Recovery for Intel Integrated Core Logic

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W305BH 数据手册

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W305B  
Frequency Controller with System Recovery for Intel£ Integrated  
Core Logic  
• Thirteen copies of SDRAM clock  
Features  
• Eight copies of PCI clock  
• Single chip FTG solution for Intel Solano/810E/810  
• One copy of synchronous APIC clock  
• Programmable clock output frequency with less than  
1 MHz increment  
• Three copies of 66-MHz outputs  
• Three copies of 48-MHz outputs  
• Integrated fail-safe Watchdog timer for system  
recovery  
• One copy of double strength 14.31818-MHz reference  
clock  
• Automatically switch to HW selected or SW  
programmed clock frequency when Watchdog timer  
time-out  
• One RESET output for system recovery  
• SMBus interface for turning off unused clocks  
• Capable of generating system RESET after a Watchdog  
timer time-out occurs or a change in output frequency  
via SMBus interface  
Key Specifications  
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps  
• Support SMBus byte read/write and block read/write  
operations to simplify system BIOS development  
APIC, 48-MHz, 3V66, PCI Outputs  
Cycle-to-Cycle Jitter:................................................... 500 ps  
• Vendor ID and Revision ID support  
CPU, 3V66 Output Skew: ........................................... 175 ps  
SDRAM, APIC, 48-MHz Output Skew: ....................... 250 ps  
PCI Output Skew: ....................................................... 500 ps  
CPU to SDRAM Skew (@ 133 MHz) ....................... 0.5 ns  
CPU to SDRAM Skew (@ 100 MHz)................. 4.5 to 5.5 ns  
CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns  
3V66 to PCI Skew (3V66 lead).......................... 1.5 to 3.5 ns  
PCI to APIC Skew..................................................... 0.5 ns  
• Programmable drive strength for SDRAM and PCI  
output clocks  
• Programmable output skew between CPU, AGP, PCI  
and SDRAM  
• Maximized EMI suppression using Cypress’s Spread  
Spectrum Technology  
• Low jitter and tightly controlled clock skew  
• Two copies of CPU clock  
Pin Configuration[1]  
Block Diagram  
GND  
VDDQ3  
REF2X/FS3^  
X1  
X2  
VDDQ3  
3V66_0  
3V66_1  
3V66_2  
GND  
PCI0/FS0^  
PCI1/FS1^  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
VDDQ2  
APIC  
GND  
VDDQ2  
CPU0  
CPU1  
GND  
SDRAM0  
SDRAM1  
SDRAM2  
VDDQ3  
GND  
SDRAM3  
SDRAM4  
SDRAM5  
SDRAM6  
VDDQ3  
GND  
SDRAM7  
SDRAM8  
SDRAM9  
SDRAM10  
VDDQ3  
GND  
SDRAM11  
SDRAM12  
RST#  
1
2
3
4
5
6
7
8
VDDQ3  
REF2X/FS3  
X1  
X2  
XTAL  
OSC  
PLL REF FREQ  
VDDQ2  
CPU0:1  
Divider,  
Delay,  
and  
9
2
SDATA  
SCLK  
SMBus  
Logic  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Phase  
Control  
Logic  
PCI2/FS2^  
GND  
APIC  
(FS0:4)  
VDDQ3  
PCI3  
PCI4  
VDDQ3  
PCI5  
PCI6  
PCI7  
GND  
48MHz  
3V66_0:2  
PCI0/FS0  
3
PLL 1  
PCI1/FS1  
PCI2/FS2  
PCI3:7  
5
48MHz/FS4^  
24_48MHz/SEL24_48MHz#*  
SDRAM0:12  
RST#  
13  
25  
26  
27  
28  
VDDQ3  
SDATA  
GND  
VDDQ3  
SCLK  
VDDQ3  
48MHz  
48MHz/FS4  
PLL2  
24_48MHz/SEL24_48MHz#  
/2  
1. Internal 100K pull-up and 100K pull-down resistors present on inputs marked with * and ^ respectively. Design should not rely solely on internal pull-up resistor  
to set I/O pins HIGH or LOW.  
Rev 1.0, November 20, 2006  
Page 1 of 20  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  
1234567...20

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