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W29EE512T-70 PDF预览

W29EE512T-70

更新时间: 2024-11-07 22:36:39
品牌 Logo 应用领域
华邦 - WINBOND 闪存存储内存集成电路光电二极管
页数 文件大小 规格书
22页 291K
描述
64K X 8 CMOS FLASH MEMORY

W29EE512T-70 技术参数

生命周期:Obsolete零件包装代码:TSOP1
包装说明:TSOP1, TSSOP32,.8,20针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.81
Is Samacsys:N最长访问时间:70 ns
其他特性:HARDWARE AND SOFTWARE DATA PROTECTION; 10-YEARS DATA RETENTION; 1K PROGRAM/ERASE CYCLE命令用户界面:NO
数据轮询:YES数据保留时间-最小值:10
耐久性:1000 Write/Erase CyclesJESD-30 代码:R-PDSO-G32
长度:18.4 mm内存密度:524288 bit
内存集成电路类型:FLASH内存宽度:8
功能数量:1部门数/规模:512
端子数量:32字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX8封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装等效代码:TSSOP32,.8,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
页面大小:128 words并行/串行:PARALLEL
电源:5 V编程电压:5 V
认证状态:Not Qualified座面最大高度:1.2 mm
部门规模:128最大待机电流:0.0001 A
子类别:Flash Memories最大压摆率:0.05 mA
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL切换位:YES
类型:NOR TYPE宽度:8 mm
最长写入周期时间 (tWC):10 msBase Number Matches:1

W29EE512T-70 数据手册

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W29EE512  
´ 8 CMOS FLASH MEMORY  
64K  
GENERAL DESCRIPTION  
The W29EE512 is a 512K bit, 5-volt only CMOS flash memory organized as 64K ´ 8 bits. The device  
can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not  
required. The unique cell architecture of the W29EE512 results in fast program/erase operations with  
extremely low current consumption (compared to other comparable 5-volt flash memory products). The  
device can also be programmed and erased using standard EPROM programmers.  
FEATURES  
· Single 5-volt program and erase operations  
· Fast page-write operations  
· Low power consumption  
- Active current: 50 mA (max.)  
- Standby current: 100 mA (max.)  
- 128 bytes per page  
· Automatic program timing with internal VPP  
generation  
- Page program cycle: 10 mS (max.)  
- Effective byte-program cycle time: 39 mS  
- Optional software-protected data write  
· Fast chip-erase operation: 50 mS  
· Read access time: 70/90/120 nS  
· Typical page program/erase cycles: 1K/10K  
· Ten-year data retention  
· End of program detection  
- Toggle bit  
- Data polling  
· Latched address and data  
· TTL compatible I/O  
· JEDEC standard byte-wide pinouts  
· Software and hardware data protection  
· Available packages: 32-pin PLCC, TSOP and  
VSOP  
Publication Release Date: February 18, 2002  
- 1 -  
Revision A7  

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