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W29C512AT-90 PDF预览

W29C512AT-90

更新时间: 2024-11-19 22:20:19
品牌 Logo 应用领域
华邦 - WINBOND 闪存存储内存集成电路光电二极管
页数 文件大小 规格书
20页 262K
描述
64 K x 8 CMOS FLASH MEMORY

W29C512AT-90 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSOP1包装说明:TSOP1-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.92Is Samacsys:N
最长访问时间:90 ns命令用户界面:NO
数据轮询:YES耐久性:1000 Write/Erase Cycles
JESD-30 代码:R-PDSO-G32JESD-609代码:e0
长度:18.4 mm内存密度:524288 bit
内存集成电路类型:FLASH内存宽度:8
功能数量:1部门数/规模:512
端子数量:32字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX8封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装等效代码:TSSOP32,.8,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
页面大小:128 words并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
编程电压:5 V认证状态:Not Qualified
座面最大高度:1.2 mm部门规模:128
最大待机电流:0.0001 A子类别:Flash Memories
最大压摆率:0.05 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
切换位:YES类型:NOR TYPE
宽度:8 mm最长写入周期时间 (tWC):10 ms
Base Number Matches:1

W29C512AT-90 数据手册

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W29C512A  
´ 8 CMOS FLASH MEMORY  
64K  
GENERAL DESCRIPTION  
The W29C512A is a 512K bit, 5-volt only CMOS flash memory organized as 64K ´ 8 bits. The device  
can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not  
required. The unique cell architecture of the W29C512A results in fast program/erase operations with  
extremely low current consumption (compared to other comparable 5-volt flash memory products). The  
device can also be programmed and erased using standard EPROM programmers.  
FEATURES  
· Single 5-volt program and erase operations  
· Fast page-write operations  
· Low power consumption  
- Active current: 50 mA (max.)  
- Standby current: 100 mA (max.)  
- 128 bytes per page  
· Automatic program timing with internal VPP  
generation  
- Page program cycle: 10 mS (max.)  
- Effective byte-program cycle time: 39 mS  
- Optional software-protected data write  
· Fast chip-erase operation: 50 mS  
· Read access time: 90 nS  
· End of program detection  
- Toggle bit  
- Data polling  
· Latched address and data  
· TTL compatible I/O  
· Typical page program/erase cycles: 1K (typ.)  
· Ten-year data retention  
· JEDEC standard byte-wide pinouts  
· Available packages: 32-pin PLCC and TSOP  
· Software and hardware data protection  
Publication Release Date: February 5, 2002  
- 1 -  
Revision A2  

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