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W29C102P-90B PDF预览

W29C102P-90B

更新时间: 2024-11-08 03:17:55
品牌 Logo 应用领域
华邦 - WINBOND 闪存存储内存集成电路
页数 文件大小 规格书
21页 253K
描述
64K 16 CMOS FLASH MEMORY

W29C102P-90B 技术参数

生命周期:Obsolete零件包装代码:LCC
包装说明:QCCJ,针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.59
Is Samacsys:N最长访问时间:90 ns
其他特性:10K PROGRAM/ ERASE CYCLE; DATA RETENTION= 10 YEARS数据保留时间-最小值:10
JESD-30 代码:S-PQCC-J44长度:16.5862 mm
内存密度:1048576 bit内存集成电路类型:FLASH
内存宽度:16功能数量:1
端子数量:44字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX16封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
编程电压:5 V认证状态:Not Qualified
座面最大高度:4.7 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
类型:NOR TYPE宽度:16.5862 mm
最长写入周期时间 (tWC):10 msBase Number Matches:1

W29C102P-90B 数据手册

 浏览型号W29C102P-90B的Datasheet PDF文件第2页浏览型号W29C102P-90B的Datasheet PDF文件第3页浏览型号W29C102P-90B的Datasheet PDF文件第4页浏览型号W29C102P-90B的Datasheet PDF文件第5页浏览型号W29C102P-90B的Datasheet PDF文件第6页浏览型号W29C102P-90B的Datasheet PDF文件第7页 
W29C102  
64K ´ 16 CMOS FLASH MEMORY  
GENERAL DESCRIPTION  
The W29C102 is a 1-megabit, 5-volt only CMOS flash memory organized as 64K ´ 16 bits. The  
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is  
not required. The unique cell architecture of the W29C102 results in fast program/erase operations  
with extremely low current consumption (compared to other comparable 5-volt flash memory  
products). The device can also be programmed and erased using standard EPROM programmers.  
FEATURES  
· Single 5-volt program and erase operations  
· Fast page-write operations  
· Low power consumption  
- Active current: 25 mA (typ.)  
- Standby current: 20 mA (typ.)  
- 128 words per page  
· Automatic program timing with internal VPP  
generation  
- Page program cycle: 10 mS (max.)  
- Effective word-program cycle time: 39 mS  
- Optional software-protected data write  
· Fast chip-erase operation: 50 mS  
· Read access time: 70/90/120 nS  
· Typical page program/erase cycles: 1K/10K  
· Ten-year data retention  
· End of program detection  
- Toggle bit  
- Data polling  
· Latched address and data  
· TTL compatible I/O  
· JEDEC standard word-wide pinouts  
· Software and hardware data protection  
· Available packages: 40-pin 600 mil DIP, TSOP  
and 44-pin PLCC  
Publication Release Date: March 1998  
- 1 -  
Revision A3  

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