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W27E020-70 PDF预览

W27E020-70

更新时间: 2024-11-21 22:06:43
品牌 Logo 应用领域
华邦 - WINBOND 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
14页 161K
描述
256K X 8 ELECTRICALLY ERASABLE EPROM

W27E020-70 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:0.600 INCH, PLASTIC, DIP-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:3A991.B.1.B.1HTS代码:8542.32.00.51
风险等级:5.92最长访问时间:70 ns
命令用户界面:NO数据轮询:NO
JESD-30 代码:R-PDIP-T32JESD-609代码:e0
长度:41.91 mm内存密度:2097152 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:32
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX8
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP32,.6封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
编程电压:12 V认证状态:Not Qualified
座面最大高度:5.33 mm最大待机电流:0.0001 A
子类别:EEPROMs最大压摆率:0.03 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED切换位:NO
宽度:15.24 mmBase Number Matches:1

W27E020-70 数据手册

 浏览型号W27E020-70的Datasheet PDF文件第2页浏览型号W27E020-70的Datasheet PDF文件第3页浏览型号W27E020-70的Datasheet PDF文件第4页浏览型号W27E020-70的Datasheet PDF文件第5页浏览型号W27E020-70的Datasheet PDF文件第6页浏览型号W27E020-70的Datasheet PDF文件第7页 
Preliminary W27E020  
256K ´ 8 ELECTRICALLY ERASABLE EPROM  
GENERAL DESCRIPTION  
The W27E020 is a high speed, low power Electrically Erasable and Programmable Read Only  
Memory organized as 262144 ´ 8 bits that operates on a single 5 volt power supply. The W27E020  
provides an electrical chip erase function.  
FEATURES  
· High speed access time:  
70/90/120 nS (max.)  
· +14V erase/+12V programming voltage  
· Fully static operation  
· Read operating current: 30 mA (max.)  
· All inputs and outputs directly TTL/CMOS  
· Erase/Programming operating current:  
compatible  
30 mA (max.)  
· Three-state outputs  
· Standby current: 1 mA (max.)  
· Single 5V power supply  
· Available packages: 32-pin 600 mil DIP and  
PLCC  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
Q0  
PGM  
CE  
Vcc  
Vpp  
A16  
A15  
A12  
A7  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
OUTPUT  
BUFFER  
1
CONTROL  
.
PGM  
A17  
2
Q7  
OE  
3
A14  
A13  
A8  
4
5
A6  
6
A0  
A5  
A9  
7
CORE  
.
A17  
A11  
DECODER  
A4  
8
ARRAY  
A3  
9
OE  
A2  
10  
11  
12  
13  
14  
A10  
A1  
CE  
Q7  
VCC  
A0  
Q6  
Q5  
Q0  
Q1  
Q2  
GND  
GND  
VPP  
18  
17  
Q4  
Q3  
15  
16  
/
A
1
6
A
1
2
A
1
5
V
p
p
V
c
c
P
A
1
7
PIN DESCRIPTION  
G
M
SYMBOL  
DESCRIPTION  
3
2
3
1
3
2
1
4
3
0
Address Inputs  
Data Inputs/Outputs  
A0- A17  
Q0- Q7  
CE  
5
6
7
8
9
10  
11  
12  
13  
29  
28  
27  
26  
25  
24  
23  
22  
21  
A14  
A13  
A8  
A9  
A11  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Q0  
Chip Enable  
32-pin PLCC  
OE  
A10  
Output Enable  
Program Enable  
OE  
1
8
1
9
2
0
CE  
Q7  
1
7
1
4
1
5
1
6
PGM  
VPP  
Program/Erase Supply Voltage  
Power Supply  
Q
2
Q
1
G
N
D
Q
3
Q
4
Q
5
Q
6
VCC  
GND  
Ground  
Publication Release Date: December 1997  
Revision A1  
- 1 -  

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