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W27C020PM-12 PDF预览

W27C020PM-12

更新时间: 2024-11-17 22:08:03
品牌 Logo 应用领域
华邦 - WINBOND 内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
14页 162K
描述
256K X 8 ELECTRICALLY ERASABLE EPROM

W27C020PM-12 技术参数

生命周期:Obsolete零件包装代码:QFJ
包装说明:QCCJ,针数:32
Reach Compliance Code:unknownECCN代码:3A991.B.1.B.1
HTS代码:8542.32.00.51风险等级:5.84
Is Samacsys:N最长访问时间:120 ns
JESD-30 代码:R-PQCC-J32长度:13.97 mm
内存密度:2097152 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:32字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX8封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:RECTANGULAR
封装形式:CHIP CARRIER并行/串行:PARALLEL
编程电压:12 V认证状态:Not Qualified
座面最大高度:3.56 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:11.43 mmBase Number Matches:1

W27C020PM-12 数据手册

 浏览型号W27C020PM-12的Datasheet PDF文件第2页浏览型号W27C020PM-12的Datasheet PDF文件第3页浏览型号W27C020PM-12的Datasheet PDF文件第4页浏览型号W27C020PM-12的Datasheet PDF文件第5页浏览型号W27C020PM-12的Datasheet PDF文件第6页浏览型号W27C020PM-12的Datasheet PDF文件第7页 
Preliminary W27C020M  
256K ´ 8 ELECTRICALLY ERASABLE EPROM  
GENERAL DESCRIPTION  
The W27C020M is a high speed, low power Electrically Erasable and Programmable Read Only  
Memory organized as 262144 ´ 8 bits that operates on a single 5 volt power supply. The W27C020M  
provides an electrical chip erase function.The W27C020M is designed to be used in 3.3V I/O bus  
interface enviornment.  
FEATURES  
· High speed access time:  
70/90/120 nS (max.)  
· +14V erase/+12V programming voltage  
· Fully static operation  
· Read operating current: 30 mA (max.)  
· Output level : 3.3V compatible output  
· Erase/Programming operating current:  
30 mA (max.)  
· All inputs and outputs directly TTL/CMOS  
compatible  
· Standby current: 1 mA (max.)  
· Single 5V power supply  
· Three-state outputs  
· Available packages: 32-pin 600 mil DIP and  
PLCC  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
Q0  
PGM  
CE  
Vcc  
Vpp  
A16  
A15  
A12  
A7  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
1
OUTPUT  
BUFFER  
CONTROL  
PGM  
A17  
2
.
Q7  
3
OE  
A14  
A13  
A8  
4
5
A6  
6
A0  
.
A5  
A9  
7
32-pin DIP  
CORE  
A11  
A4  
8
DECODER  
ARRAY  
A3  
9
OE  
A17  
A2  
10  
11  
12  
13  
14  
A10  
A1  
CE  
Q7  
A0  
VCC  
Q6  
Q5  
Q4  
Q3  
Q0  
Q1  
Q2  
GND  
GND  
VPP  
18  
17  
15  
16  
PIN DESCRIPTION  
/
A
1
6
A
1
2
A
1
5
V
p
p
V
c
c
P
A
1
7
G
M
SYMBOL  
DESCRIPTION  
Address Inputs  
Data Inputs/Outputs  
A0- A17  
Q0- Q7  
CE  
3
2
3
1
4
3
2
1
3
0
5
6
7
8
9
10  
11  
12  
13  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Q0  
29  
28  
27  
26  
25  
24  
23  
22  
21  
A14  
A13  
A8  
A9  
A11  
Chip Enable  
32-pin PLCC  
OE  
A10  
Output Enable  
Program Enable  
OE  
1
8
1
9
2
0
CE  
Q7  
1
7
1
4
1
5
1
6
PGM  
VPP  
Program/Erase Supply Voltage  
Power Supply  
Q
1
Q G Q Q Q  
Q
6
2
N
D
3 4 5  
VCC  
GND  
Ground  
Publication Release Date: March 1999  
Revision A1  
- 1 -  

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