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W24LH8Q-55LE PDF预览

W24LH8Q-55LE

更新时间: 2024-11-13 21:55:23
品牌 Logo 应用领域
华邦 - WINBOND 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
10页 198K
描述
Normal speed, Very low power CMOS static RAM Organized as 32768 x 8 bits

W24LH8Q-55LE 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP包装说明:TSSOP, TSSOP28,.53,22
针数:28Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.92最长访问时间:100 ns
其他特性:55 NANO SECOND ACCESS TIME WITH 5V NOMINAL SUPPLYI/O 类型:COMMON
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:11.8 mm内存密度:262144 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端子数量:28
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-20 °C组织:32KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP28,.53,22
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3/5 V认证状态:Not Qualified
座面最大高度:1.2 mm最小待机电流:2 V
子类别:SRAMs最大压摆率:0.07 mA
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:8 mm
Base Number Matches:1

W24LH8Q-55LE 数据手册

 浏览型号W24LH8Q-55LE的Datasheet PDF文件第2页浏览型号W24LH8Q-55LE的Datasheet PDF文件第3页浏览型号W24LH8Q-55LE的Datasheet PDF文件第4页浏览型号W24LH8Q-55LE的Datasheet PDF文件第5页浏览型号W24LH8Q-55LE的Datasheet PDF文件第6页浏览型号W24LH8Q-55LE的Datasheet PDF文件第7页 
W24LH8  
´ 8 CMOS STATIC RAM  
32K  
GENERAL DESCRIPTION  
The W24LH8 is a normal speed, very low power CMOS static RAM organized as 32768 ´ 8 bits that  
operates on a wide voltage range from 2.7V to 5.5V power supply. The W24LH8 family, W24LH8-55LE  
and W24LH8-55LI, can meet requirement of various operating temperature. This device is  
manufactured using Winbond's high performance CMOS technology.  
FEATURES  
· Low power consumption  
· Access time: 55 nS (5V ±10%),  
100 nS (3V ±10%)  
· Three-state outputs  
· Battery back-up operation capability  
· Data retention voltage: 2V (min.)  
· Available packages: 330 mil SOP and standard  
type one TSOP (8 mm ´ 13.4 mm)  
· 2.7V to 5.5V supply voltage  
· Fully static operation  
· All inputs and outputs directly TTL compatible  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
CLK GEN.  
PRECHARGE CKT.  
A12  
A14  
A2  
R
O
A14  
A12  
A7  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VDD  
#WE  
A13  
A8  
W
CORE CELL ARRAY  
512 ROWS  
2
A3  
D
E
C
O
D
E
R
3
A4  
64 X 8 COLUMNS  
A6  
A5  
4
A5  
5
A9  
A6  
A4  
6
A11  
#OE  
A10  
#CS  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
A7  
28-pin  
SOP  
A3  
7
A13  
I/O1  
I/O8  
A2  
8
I/O CKT.  
COLUMN DECODER  
DATA  
CNTRL.  
A1  
9
CLK  
GEN.  
A0  
10  
11  
12  
13  
14  
I/O1  
I/O2  
A10 A1 A0 A8 A9  
A11  
#WE  
#CS  
#OE  
I/O3  
V
SS  
PIN DESCRIPTION  
A10  
#OE  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
SYMBOL  
DESCRIPTION  
2
#CS  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
A11  
3
A9  
Address Inputs  
4
A0- A14  
I/O1- I/O8  
#CS  
A8  
A13  
5
6
#WE  
Data Inputs/Outputs  
Chip Select Input  
Write Enable Input  
Output Enable Input  
Power Supply  
28-pin  
TSOP  
7
V
DD  
8
A14  
A12  
A7  
A6  
A5  
A4  
A3  
V
SS  
9
I/O3  
I/O2  
I/O1  
A0  
A1  
A2  
10  
11  
12  
13  
14  
#WE  
#OE  
VDD  
VSS  
Ground  
Publication Release Date: March 2001  
Revision A3  
- 1 -  

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