W238
FTG for Integrated Core Logic with 133-MHz FSB
APIC, 48-MHz, SDRAM Output Skew:........................250 ps
Features
CPU, 3V66 Output Skew:............................................175 ps
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Two copies of CPU clock at 66/100/133 MHz
• Thirteen copies of SDRAM clocks at 100/133 MHz
• Five copies of PCI clock compliant to PCI spec 2-1 and
capable of driving a maximum load of 40pf
PCI Output Skew:........................................................500 ps
CPU to SDRAM Skew (@ 133 MHz):.........................±0.5 ns
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to APIC Skew: .....................................................±0.5 ns
Table 1. Pin Selectable Functions
• One copy of synchronous APIC clock
• Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
• Three copies of 66-MHz fixed clock
• One copy of 14.31818-MHz reference clock
• Power down control
Tristate# FSEL1 FSEL0
Function
SDRAM
0
0
1
1
1
1
X
X
0
0
1
1
0
1
0
1
0
1
Three -State Three-State
Test
Test
66 MHz
100 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
• SMBus interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
Pin Configuration[1]
Block Diagram
VDDQ3
APIC
VDDQ2
GND
56
GND
VDDQ2
CPU0
CPU1
GND
SDRAM0
SDRAM1
1
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
REF/FSEL1
3
X1
X2
XTAL
OSC
REF/FSEL1
VDDQ3
X1
4
5
PLL REF FREQ
6
VDDQ2
X2
GND
7
Divider,
Delay,
and
Phase
Control
Logic
8
VDDQ3
GND
VDDQ3
3V66_0
3V66_1
3V66_AGP
GND
PCI_ICH
PCI1
9
SDATA
SCLK
SMBus
Logic
CPU0:1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
GND
SDRAM6
SDRAM7
SDRAM8
SDRAM9
VDDQ3
GND
SDRAM10
SDRAM11
VDDQ3
GND
SDRAM12
PWRDWN#/TRISTATE#
DOT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
2
APIC0:1
VDDQ3
PLL 1
3V66_0:1
3V66_AGP
PCI0_ICH
FSEL0:1
PCI2
VDDQ3
GND
PCI3
PCI4
2
PCI1:4
FSEL0
GNDA
VDDA
SCLK
4
SDRAM0:12
13
SDATA
25
26
27
28
PWRDWN#/TRISTATE#
GND
VDDQ3
USB
VDDQ3
USB
PLL2
Note:
1. Internal pull-down resistors present on input marked with *.
Design should not solely rely on internal pull-down resister to
set I/O pin LOW.
DOT
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07219 Rev. *A*
Revised December 15, 2002