5秒后页面跳转
捷配首页

Datasheet > 微控制器和处理器 > 时钟发生器> W209BH
W209BH PDF预览

W209BH

更新时间： 2024-11-19 13:15:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
16页 174K
描述
Processor Specific Clock Generator, CMOS, PDSO48, 0.300 INCH, SSOP-48

阅读下载

中文翻译

获取价格

W209BH 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.77
Is Samacsys：NJESD-30 代码：R-PDSO-G48
JESD-609代码：e0长度：15.875 mm
端子数量：48封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH认证状态：Not Qualified
座面最大高度：2.794 mm表面贴装：YES
技术：CMOS端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL宽度：7.5 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

W209BH 数据手册

 浏览型号W209BH的Datasheet PDF文件第2页浏览型号W209BH的Datasheet PDF文件第3页浏览型号W209BH的Datasheet PDF文件第4页浏览型号W209BH的Datasheet PDF文件第5页浏览型号W209BH的Datasheet PDF文件第6页浏览型号W209BH的Datasheet PDF文件第7页 
PRELIMINARY  
W209C  
Frequency Generator for Integrated Core Logic  
with 133-MHz FSB  
Features  
Table 1. Frequency Selections  
FS4 FS3 FS2 FS1 FS0 CPU SDRAM 3V66 PCI APIC  
SS  
OFF  
–0.6%  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
• Maximized EMI suppression using Cypress’s Spread  
Spectrum technology  
• Low jitter and tightly controlled clock skew  
• Highly integrated device providing clocks required for  
CPU, core logic, and SDRAM  
• Two copies of CPU clock  
• Nine copies of SDRAM clock  
• Eight copies of PCI clock  
• One copy of synchronous APIC clock  
• Two copies of 66-MHz outputs  
• Two copies of 48-MHz outputs  
• One copy of selectable 24- or 48-MHz clock  
• One copy of double strength 14.31818-MHz reference  
clock  
• Power-down control  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
75.3  
95.0  
113.0  
95.0  
75.3 37.6 18.8  
63.3 31.6 15.8  
86.0 43.0 21.5  
75.3 37.6 18.8  
129.0 129.0  
150.0 113.0  
150.0 150.0 100.0 50.0 25.0  
110.0  
110.0  
73.0 36.6 18.3  
93.3 46.7 23.3  
72.0 36.0 18.0  
68.3 34.1 17.0  
70.0 35.0 17.5  
92.0 46.0 23.0  
70.0 35.0 17.5  
140.0 140.0  
144.0 108.0  
68.3  
102.5  
105.0 105.0  
138.0 138.0  
140.0 105.0  
66.8  
100.2  
66.8 33.4 16.7 ±0.45%  
66.8 33.4 16.7 ±0.45%  
89.1 44.4 22.2 ±0.45%  
66.8 33.4 16.7 ±0.45%  
100.2 100.2  
133.6 133.6  
133.6 100.2  
157.3 118.0  
160.0 120.0  
146.6 110.0  
• SMBus interface for turning off unused clocks  
78.6 39.3 19.6  
80.0 40.0 20.0  
73.3 36.6 18.3  
61.0 30.5 15.2  
84.6 42.3 21.1  
81.3 40.6 20.3  
78.0 39.0 19.5  
76.0 38.0 19.0  
80.0 40.0 20.0  
78.0 39.0 19.5  
55.3 27.6 13.8  
53.3 26.7 13.3  
66.6 33.3 16.6  
66.6 33.3 16.6  
88.9 44.4 22.2  
66.6 33.3 16.6  
OFF  
OFF  
Key Specifications  
OFF  
122.0  
91.5  
–0.6%  
OFF  
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps  
127.0 127.0  
122.0 122.0  
APIC, 48-MHz, 3V66, PCI Outputs  
Cycle-to-Cycle Jitter:................................................... 500 ps  
–0.6%  
OFF  
117.0  
114.0  
80.0  
117.0  
114.0  
120.0  
117.0  
CPU, 3V66 Output Skew: ........................................... 175 ps  
SDRAM, APIC, 48-MHz Output Skew: ....................... 250 ps  
PCI Output Skew: ....................................................... 500 ps  
CPU to SDRAM Skew (@ 133 MHz) ....................... ± 0.5 ns  
CPU to SDRAM Skew (@ 100 MHz)................. 4.5 to 5.5 ns  
CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns  
3V66 to PCI Skew (3V66 lead).......................... 1.5 to 3.5 ns  
PCI to APIC Skew..................................................... ± 0.5 ns  
OFF  
OFF  
78.0  
OFF  
166.0 166.0  
160.0 160.0  
OFF  
OFF  
66.6  
100.0  
–0.6%  
–0.6%  
–0.6%  
–0.6%  
100.0 100.0  
133.3 133.3  
133.3 100.0  
VDDQ3  
Pin Configuration[1]  
Block Diagram  
REF2X/FS3*  
X1  
X2  
XTAL  
OSC  
VDDQ2  
APIC  
VDDQ2  
CPU0  
CPU1  
GND  
VDDQ3  
SDRAM0  
SDRAM1  
SDRAM2  
GND  
SDRAM3  
SDRAM4  
SDRAM5  
VDDQ3  
SDRAM6  
SDRAM7  
DCLK  
GND  
PWRDWN#  
SCLK  
REF2x/FS3*  
VDDQ3  
X1  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
PLL REF FREQ  
2
VDDQ2  
CPU0:1  
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
X2  
Divider,  
Delay,  
and  
Phase  
Control  
Logic  
GND  
2
SDATA  
SCLK  
SMBus  
Logic  
VDDQ3  
3V66_0  
3V66_1  
GND  
FS0*/PCI0  
FS1*/PCI1  
FS2*/PCI2  
GND  
PCI3  
PCI4  
VDDQ3  
PCI5  
APIC  
(FS0:4*)  
VDDQ3  
3V66_0:1  
2
FS0*/PCI0  
PLL 1  
FS1*/PCI1  
FS2*/PCI2  
PCI3:7  
PCI6  
PCI7  
GND  
5
8
SDRAM0:7  
DCLK  
^
PWRDWN#  
48MHz_0  
FS4*/48MHz_1  
SI0/24_48#MHz*  
VDDQ3  
VDDQ3  
GND  
SDATA  
VDDQ3  
48MHz_0  
Note:  
FS4*/48MHz_1  
PLL2  
1. Internal pull-down or pull-up resistors present on inputs marked with  
* or ^ respectively. Design should not rely solely on internal pull-up  
or pull-down resistor to set I/O pins HIGH or LOW respectively.  
SI0/24_48#MHz*  
/2  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-07171 Rev. *A  
Revised December 15, 2002  
1234567...16

中文翻译

下载PDF

与W209BH相关器件

型号 品牌 获取价格 描述 数据表
W209C SPECTRALINEAR

获取价格

 		Frequency Generator for Integrated Core Logic with 133MHz FSB
W209C CYPRESS

获取价格

 		Frequency Generator for Integrated Core Logic with 133-MHz FSB
W209CH CYPRESS

获取价格

 		Frequency Generator for Integrated Core Logic with 133-MHz FSB
W209CHT SILICON

获取价格

 		Processor Specific Clock Generator, 166MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48
W20NK70Z STMICROELECTRONICS

获取价格

 		N-CHANNEL 700V - 0.25W - 20A TO-247 Zener-Protected SuperMESH TM Power MOSFET
W20NM60FD STMICROELECTRONICS

获取价格

 		N-CHANNEL 600V - 0.26ohm - 20A TO-220-TO-220FP-TO-247 FDmesh POWER MOSFET (with FAST DIODE
W20S100K2 WALL

获取价格

 		Power Management Circuit,
W20S100K2M WALL

获取价格

 		Power Management Circuit,
W20S100N WALL

获取价格

 		Power Management Circuit,
W20S100NM WALL

获取价格

 		Power Management Circuit,

与W209BH相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证