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W144 PDF预览

W144

更新时间: 2024-11-05 03:18:07
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SPECTRALINEAR /
页数 文件大小 规格书
13页 201K
描述
440BX AGPset Spread Spectrum Frequency Synthesizer

W144 数据手册

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W144  
440BX AGPset Spread Spectrum Frequency Synthesizer  
Table 1. Pin Selectable Frequency  
Features  
Input Address  
• Maximized electromagnetic interference (EMI)  
suppression using Cypress’ Spread Spectrum  
technology  
• Single chip system frequency synthesizer for Intel®  
440BX AGPset  
CPU_F, CPU1  
(MHz)  
FS3 FS2 FS1 FS0  
PCI_F, 1:5 (MHz)  
33.4 (CPU/4)  
31 (CPU/4)  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
133.6  
124  
150  
140  
105  
110  
37.5 (CPU/4)  
35 (CPU/4)  
• Two copies of CPU output  
• Six copies of PCI output 1  
• One 48 MHz output for USB  
• One 24 MHz output for SIO  
• Two buffered reference outputs  
• One IOAPIC output  
35 (CPU/3)  
36.7 (CPU/3)  
38.3 (CPU/3)  
40 (CPU/3)  
115  
120  
100.2  
133.3  
112  
33.4 (CPU/3)  
44.43 (CPU/3)  
37.3 (CPU/3)  
34.3 (CPU/3)  
33.4 (CPU/2)  
41.7 (CPU/2)  
37.5 (CPU/2)  
41.3 (CPU/3)  
• Thirteen SDRAM outputs provide support for three  
DIMMs  
103  
66.8  
83.3  
75  
• Supports frequencies up to 150 MHz  
• I2C interface for programming  
• Power management control inputs  
124  
Pin Configuration[1]  
Logic Block Diagram  
VDDQ3  
VDDQ3  
REF0/(PCI_STOP#)  
GND  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDQ2  
IOAPIC  
REF1/FS2*  
GND  
CPU_F  
CPU1  
VDDQ2  
CLK_STOP#  
SDRAM_F  
GND  
SDRAM0  
SDRAM1  
VDDQ3  
SDRAM2  
SDRAM3  
GND  
SDRAM4  
SDRAM5  
VDDQ3  
SDRAM6  
SDRAM7  
VDDQ3  
1
2
3
4
5
6
7
8
REF0/(PCI_STOP#)  
REF1/FS2  
X1  
X2  
XTAL  
OSC  
X1  
X2  
PLL Ref Freq  
VDDQ2  
IOAPIC  
VDDQ3  
PCI_F/MODE  
**PCI1/FS3  
GND  
Stop  
Clock  
Control  
I/O Pin  
Control  
9
PCI2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
CLK_STOP#  
VDDQ2  
PCI3  
PCI4  
PCI5  
Stop  
Clock  
Control  
CPU1  
PLL 1  
VDDQ3  
SDRAMIN  
GND  
CPU_F  
÷2,3,4  
VDDQ3  
PCI_F/MODE  
PCI1/FS3  
PCI2  
SDRAM11  
SDRAM10  
VDDQ3  
SDRAM9  
SDRAM8  
GND  
Stop  
Clock  
Control  
PCI3  
PCI4  
PCI5  
I2C  
{
SDATA  
SCLK  
48MHz/FS0*  
24MHz/FS1*  
I2C  
Logic  
SDATA  
SCLK  
VDDQ3  
48MHz/FS0  
PLL2  
÷2  
24MHz/FS1  
VDDQ3  
SDRAM0:11  
Stop  
Clock  
Control  
SDRAMIN  
12  
SDRAM_F  
Note:  
1. * Has an internal pull-up resistors. It should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping  
while ** has an internal pull down resistor.  
Rev 1.0, November 21, 2006  
Page 1 of 13  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  

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