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VSP5010PM PDF预览

VSP5010PM

更新时间: 2024-11-15 12:17:11
品牌 Logo 应用领域
德州仪器 - TI 模拟IC信号电路
页数 文件大小 规格书
25页 711K
描述
12-Bit, 31-MSPS, Dual-Channel CCD ANALOG FRONT-END FOR DIGITAL COPIERS

VSP5010PM 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QFP
包装说明:GREEN, PLASTIC, LQFP-64针数:64
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.55Is Samacsys:N
模拟集成电路 - 其他类型:IMAGE SENSORJESD-30 代码:S-PQFP-G64
JESD-609代码:e6长度:10 mm
湿度敏感等级:1功能数量:1
端子数量:64最高工作温度:85 °C
最低工作温度:-25 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Bismuth (Sn/Bi)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

VSP5010PM 数据手册

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VSP5010  
www.ti.com ................................................................................................................................................................................................ SBES014AUGUST 2008  
12-Bit, 31-MSPS, Dual-Channel  
CCD ANALOG FRONT-END FOR DIGITAL COPIERS  
1
FEATURES  
APPLICATIONS  
Copiers  
Scanners  
Facsimiles  
2
Dual-Channel CCD Processing:  
Correlated Double Sampler (CDS)  
Sample-and-Hold Mode (S/H)  
Digital Programmable Amplifier  
CCD Offset Correction (OB Loop)  
DESCRIPTION  
The VSP5010 is a complete application-specific  
standard product (ASP) for charge-coupled device  
(CCD) line sensor applications such as copiers,  
scanners, and facsimiles. The VSP5010 provides two  
independent line-processing channels, and performs  
analog front-end (AFE) data processing and  
analog-to-digital conversion. Each channel features  
High-Performance ADC:  
12-Bit Resolution  
INL: ±2 LSB  
DNL: ±0.5 LSB  
No Missing Codes Ensured  
correlated  
double  
sampling  
(CDS)  
and  
High-Speed Operation:  
sample-and-hold (S/H) processing stages, 14  
analog-to-digital converter (ADC) blocks, a digital  
programmable gain amplifier (DPGA), and an optical  
black (OB) correction loop. Data are output in a 12-bit  
word; two-channel ADC data are multiplexed and  
then output.  
Sample Rate: 31 MHz (max, Design  
Ensured)  
78-dB SNR (at 0-dB Gain)  
Low-Power Consumption:  
Low Voltage: 3.0 V to 3.6 V  
Low Power: 290 mW (typ at 3.3 V)  
Standby Mode: 20 mW (typ)  
The VSP5010 operates from a single 3.3-V supply.  
The device is available in an LQFP-64 package.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCT PREVIEW information concerns products in the  
formative or design phase of development. Characteristic data and  
other specifications are design goals. Texas Instruments reserves  
the right to change or discontinue these products without notice.  
Copyright © 2008, Texas Instruments Incorporated  

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