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VSP3200Y/2K PDF预览

VSP3200Y/2K

更新时间: 2024-11-13 22:06:11
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页数 文件大小 规格书
16页 352K
描述
CCD SIGNAL PROCESSOR FOR SCANNER APPLICATIONS

VSP3200Y/2K 数据手册

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VSP3200  
VSP3210  
VSP3200  
www.ti.com  
CCD SIGNAL PROCESSOR FOR  
SCANNER APPLICATIONS  
FEATURES  
DESCRIPTION  
The VSP3200 and VSP3210 are complete CCD image  
processors that operate from single +5V supplies.  
F INTEGRATED TRIPLE-CORRELATED  
DOUBLE SAMPLER  
F OPERATION MODE SELECTABLE:  
This complete image processor includes three Corre-  
lated Double Samplers (CDSs) and Programmable  
Gain Amplifiers (PGAs) to process CCD signals.  
1-Channel, 3-Channel CCD Mode, 8Msps  
F PROGRAMMABLE GAIN AMPLIFIER:  
0dB to +13dB  
The VSP3200 is interface compatible with the  
VSP3210, which is a 16-bit, one-chip product.  
F SELECTABLE OUTPUT MODES:  
Normal/Demultiplexed  
The VSP3210 is pin-to-pin compatible with VSP3100,  
when in demultiplexed output mode.  
F OFFSET CONTROL RANGE: ±500mV  
F +3V, +5V Digital Output  
The VSP3200 and VSP3210 can be operated from 0°C  
to +85°C, and are available in LQFP-48 packages.  
F LOW POWER: 300mW (typ)  
F LQFP-48 SURFACE-MOUNT PACKAGE  
VREF  
CLP  
CK1 CK2  
ADCCK  
TP0  
Reference  
Circuit  
CM  
Timing Generator  
Clamp  
Clamp  
Clamp  
REFP  
REFN  
RINP  
CDS  
CDS  
CDS  
PGA  
PGA  
PGA  
AGND  
6
OE  
10  
10  
10  
10-Bit  
DAC  
VDRV  
16-Bit  
A/D  
Converter  
Digital  
Output  
Control  
GINP  
B0-B15  
(A0-A2, D0-D9)  
MUX  
16  
6
10-Bit  
DAC  
BINP  
3
Gain  
Control  
Register  
Offset  
Register  
10  
10-Bit  
DAC  
Register  
Port  
R
G
B
R
G
B
P/S  
Configuration  
Register  
WRT  
RD  
6
SCLK  
SD  
8
6
VSP3200  
Copyright © 2000, Texas Instruments Incorporated  
SBMS012A  
Printed in U.S.A. November, 2000  

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