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VSP01M01ZWDR

更新时间: 2024-11-14 11:58:27
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91页 1487K
描述
CCD Analog Front-End with Timing Generator and Vertical Driver for Digital Cameras

VSP01M01ZWDR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:TFBGA,针数:100
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.79其他特性:ALSO IT REQUIRES 2.7V TO 3.6V DIGITAL SUPPLY
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:S-PBGA-B100
JESD-609代码:e1长度:7 mm
湿度敏感等级:2功能数量:1
端子数量:100最高工作温度:85 °C
最低工作温度:-25 °C封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装形状:SQUARE
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
表面贴装:YES温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.65 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

VSP01M01ZWDR 数据手册

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VSP01M01  
VSP01M02  
www.ti.com .................................................................................................................................................................................................. SBES016MARCH 2009  
CCD Analog Front-End with Timing Generator and Vertical Driver for Digital Cameras  
1
FEATURES  
Flexible Voltage Operation:  
CCD Signal Processing:  
36-MHz Correlated Double Sampling (CDS)  
16-Bit Analog-to Digital Conversion:  
AFET + TG: 2.7 V to 3.6 V  
VL: –5.0 V to –9.0 V  
VM: GND  
36-MHz Conversion Rate  
VH: 11.5 V to 15.5 V  
No Missing Codes Ensured  
Low Power: 139 mW at 3.0 V, 36 MHz  
Stand-By + Power-Save Mode: 36 mW  
Stand-By Mode (MCK Off): 10 mW  
80-dB Input-Referred SNR (at 12-dB Gain)  
Programmable Black Level Clamping  
Programmable Gain Amplifier (PGA):  
BGA-100 Package  
–9 dB to +44 dB  
–3 dB to +18 dB by Analog Front Gain  
–6 dB to +26 dB by Digital Gain  
DESCRIPTION  
The VSP01M01 and VSP01M02 are complete  
mixed-signal ICs for charge-coupled device (CCD)  
signal processing with  
Timing Generator:  
a
built-in CCD timing  
Fully Programmable VRATE Timing by Serial  
I/O  
generator, analog-to-digital converter (ADC), and  
CCD vertical driver. The AFE CCD channel has  
correlated double sampling to extract image  
information from the CCD output signal. Signal paths  
have gains ranging from –9 dB to +44 dB. The black  
level clamping circuit enables accurate black  
reference level and quick black level recovery after  
gain changes. An input signal clamp with CDS offset  
adjustment function is available. The system  
synchronizes the master clock, horizontal driver (HD),  
and vertical driver (VD). The VSP01M01 and  
VSP01M02 support all signal terminals required by  
CCD architecture. The RG driver, HG driver, and  
vertical driver synchronize the ADC clock phase in  
order to realize ideal performance.  
Default Timing Supports Standard  
Operation  
Flexible VRATE Pin Assignment  
HD/VD Master or Slave Mode  
External Trigger, Strobe Function Support  
Flexible Draft or Pixel Summing Operation  
RG and HG Driver:  
Programmable Drivability Control  
Two Horizontal Transfer Independent  
Drivers  
One Reset Gate Driver  
CCD Horizontal High-Speed Clock Phase  
Control:  
Fine Step: 0.28 ns  
Wide Step: 1/3 Pixel Rate  
Vertical CCD Driver:  
8-Channel VDRIVER with Sub-Driver  
Supports Three-Field CCD Driving  
Three Level Drivers (VTRANSFER) × 5  
Two Level Drivers (VTRANSFER) × 3  
Two Level Drivers (ESHUTTER) × 1  
450 pF to 1890 pF with 60 to 240 Ω  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  

VSP01M01ZWDR 替代型号

型号 品牌 替代类型 描述 数据表
VSP01M01ZWD TI

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CCD Analog Front-End with Timing Generator and Vertical Driver for Digital Cameras

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