VSC7123

更新时间： 2024-02-22 04:15:04

品牌	Logo	应用领域
VITESSE		光纤以太网
页数	文件大小	规格书
18页	210K
描述
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet

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技术参数
数据手册

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VSC7123 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QFP, TQFP64,.63SQ,32	Reach Compliance Code：	unknown
风险等级：	5.92	JESD-30 代码：	S-PQFP-G64
端子数量：	64	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	TQFP64,.63SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	3.3 V	认证状态：	Not Qualified
子类别：	Other Telecom ICs	最大压摆率：	260 mA
标称供电电压：	3.3 V	表面贴装：	YES
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD

VSC7123 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

10-Bit Transceiver for Fibre

Channel and Gigabit Ethernet

VSC7123

Features

• 802.3z Gigabit Ethernet-Compliant

• Automatic Lock-to-Reference

1.25 Gb/s Transceiver

• RX Cable Equalization

• ANSI X3T11 Fibre Channel-Compliant

1.0625 Gb/s Transceiver

• Analog/Digital Signal Detection

• JTAG Access Port for Testability

• Single +3.3V Supply, 650mW Typical

• 0.98 to 1.36 Gb/s Full-Duplex Operation

• 10-Bit TTL Interface for Transmit and

Receive Data

• Packages: 64-Pin 10mm and 14mm PQFP and

10mm TQFP

General Description

The VSC7123 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard

pinouts. The VSC7123 accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK

and serializes the data onto the TX PECL differential outputs at a baud rate which is 10 times the REFCLK

frequency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit

(CRU) and deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty

clocks. The VSC7123 receiver detects “Comma” characters for frame alignment. An analog/digital signal

detection circuit indicates that a valid signal is present on the RX input. A cable equalizer compensates for

InterSymbol Interference (ISI) in order to increase maximum cable distances. The VSC7123 is a higher

performance, lower cost replacement for the VSC7125 and VSC7135.

VSC7123 Block Diagram

Serial to

Parallel

Q D

R(0:9)

RX+

RX-

2:1

÷10

÷20

Clock

Recovery

RCLK

RCLKN

Comma

Detect

COMDET

ENCDET

EWRAP

Signal

Detect

SIGDET

TX+

TX-

Parallel

to Serial

T(0:9)

D Q

x10 Clock

Multiply

REFCLK

NOT SHOWN: JTAG Boundary Scan

G52212-0, Rev 4.3

03/25//01

Page 1

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

12 3 4 5 6 7...18

中文翻译

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